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MPC905EF

P1-P3P4-P6P7-P8
DATASHEET
1:6 PCI Clock Generator/Fanout Buffer MPC905
MPC905 REVISION 4 DECEMBER 18, 2012 1 ©2012 Integrated Device Technology, Inc.
1:6 PCI Clock Generator/
Fanout Buffer
The MPC905 is a six output clock generation device targeted to provide the
clocks required in a 3.3 V or 5.0 V PCI environment. The device operates from a
3.3 V supply and can interface to either a TTL input or an external crystal. The
inputs to the device can be driven with 5.0 V when the V
CC
is at 3.3 V. The
outputs of the MPC905 meet all of the specifications of the PCI standard.
Features
• Six Low Skew Outputs
• Synchronous Output Enables for Power Management
• Low Voltage Operation
• XTAL Oscillator Interface
• 16-Lead SOIC Package
• 5.0 V Tolerant Enable Inputs
• Replacement part: ICS83905
Functional Description
The MPC905 device is targeted for PCI bus or processor bus environments
with up to 12 clock loads. Each of the six outputs on the MPC905 can drive two
series terminated 50 transmission lines. This capability effectively makes the
MPC905 a 1:12 fanout buffer.
The MPC905 offers two synchronous enable inputs to allow users flexibility in
developing power management features for their designs. Both enable signals are active HIGH inputs. A logic ‘0’ on the
ENABLE1 will pull outputs 0 to 4 into the logic ‘0’ state. A logic ‘1’ on the ENABLE1 input will result in outputs 0 to 4 to be toggling.
A logic ‘0’ on ENABLE2 will cause output BLK5 to a logic ‘0’ state, whereas a logic ‘1’ on ENABLE2 will cause output BLK5 to
toggle. The oscillator remains on.
The ENABLE2 input can be used to disable any high power device for system power savings during periods of inactivity. Both
enable inputs are synchronized internal to the chip so that the output disabling will happen only when the outputs are already
LOW. This feature guarantees no runt pulses will be generated during enabling and disabling.
1:6 PCI
CLOCK GENERATOR/
FANOUT BUFFER
SCALE 2:1
D SUFFIX
EF SUFFIX (PB-FREE PACKAGE)
PLASTIC SOIC PACKAGE
CASE 751B-05
Product Discontinuance Notice – Last Time Buy Expires on (12/7/2013)
MPC905 REVISION 4 DECEMBER 18, 2012 2 ©2012 Integrated Device Technology, Inc.
MPC905 Data Sheet 1:6 PCI CLOCK GENERATOR/FANOUT BUFFR
Figure 1. Block Diagram Figure 2. Pinout: 16-Lead Plastic Package
(Top View)
BCLK0
BCLK1
BCLK2
BCLK3
BCLK4
BCLK5
V
DD
(3) GND (3)
XTAL_IN
XTAL_OUT
ENABLE1
ENABLE2
SYNCHRONIZE
SYNCHRONIZE
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
XTAL_OUT
ENABLE2
GND1
BCLKO
V
DD1
BCLK1
GND2
BCLK2
XTAL_IN
ENABLE1
BCLK5
V
DD3
BCLK4
GND3
BCLK3
V
DD2
Table 1. Pin Configurations
Pin I/O Type Function
XTAL_IN, XTAL_OUT Input Analog Crystal Oscillator Terminals
ENABLE1, ENABLE2 Input LVCMOS Output Enable
BCLK0–BCLK5 Output LVCMOS Clock Outputs
V
DD
Supply Positive Power Supply
GND Supply Negative Power Supply
Table 2. Function Table
ENABLE1 ENABLE2 Outputs 0 to 4 Output 5 OSC (On/Off)
0
0
1
1
0
1
0
1
Low
Low
Toggling
Toggling
Low
Toggling
Low
Toggling
ON
ON
ON
ON
Table 3. Absolute Maximum Ratings
(1)
1. Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to
the Recommended Operating Conditions.
Symbol Parameter Min Max Unit
V
DD
Supply Voltage –0.5 4.6 V
V
IN
Input Voltage –0.5 V
CC
+ 0.5 V
T
oper
Operating Temperature Range 0 +70 C
T
stg
Storage Temperature Range –65 +150 C
T
sol
Soldering Temperature Range (10 Sec) +260 C
T
j
Junction Temperature Range +125 C
ESD Static Discharge Voltage 1500 V
I
Latch
Latch Up Current 50 mA
MPC905 REVISION 4 DECEMBER 18, 2012 3 ©2012 Integrated Device Technology, Inc.
MPC905 Data Sheet 1:6 PCI CLOCK GENERATOR/FANOUT BUFFR
Table 4. Recommended Operating Conditions
Symbol Parameter Min Max Unit
T
A
Ambient Temperature Range 0 70 C
V
CC
Positive Supply Voltage (Functional Range) 3.0 3.6 V
t
DC
in T
high
(at XTAL_IN Input)
T
low
(at XTAL_IN Input)
0.44T
(1)
0.44T
(1)
1. When using External Source for reference, requirement to meet PCI clock duty cycle requirement on the output.
0.56T
(1)
0.56T
(1)
T = Period
Table 5. DC Characteristics (T
A
= 0–70°C; V
DD
= 3.3 V ± 0.3 V)
Symbol Characteristic Min Typ Max Unit Condition
V
IH
High Level Input Voltage 2.0 5.5
(2)
V
V
IL
Low Level Input Voltage 0.8 V
V
OH
High Level Output Voltage 2.4 V I
OH
= –36 mA
(1)
1. The MPC905 can drive 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated transmission line to
V
TT
= V
CC
/2. Alternately, the device drives up to two 50 series terminated transmission lines per output.
V
OL
Low Level Output Voltage 0.4 V I
OL
= 36 mA
(1)
I
IH
Input High Current 2.5
(2)
2. XTAL_IN input will sink up to 10mA when driven to 5.5 V. There are no reliability concerns associated with the condition. Note that the
ENABLE1 input must be a logic HIGH. Do not take the ENABLE1 input to a logic LOW with >V
CC
volts on the XTAL_IN input.
A
I
IL
Input Low Current 2.5 A
I
CC
Power Supply Current DC
33 MHz
66 MHz
20
37
78
45
95
A
mA
mA
C
IN
Input Capacitance XTAL_IN
Others
9.0
4.5
pF
Table 6. AC Characteristics (T
A
= 0–70C; V
DD
= 3.3 V 0.3 V)
Symbol Characteristic Min Typ Max Unit Condition
F
max
Maximum Operating Using External Crystal
Frequency Using External Clock Source
—
DC
50
100
MHz
t
pw
Output Pulse Width HIGH (Above 2.0 V)
LOW (Below 0.8 V)
HIGH (Above 2.0 V)
LOW (Below 0.8 V)
0.40T
(1)
0.40T
(1)
0.45T
(2)
0.45T
(2)
1. Assuming input duty cycle specs from Recommended Operating Conditions table are met.
2. Assuming external crystal or 50% duty cycle external reference is used.
0.60T
(1)
0.60T
(1)
0.55T
(2)
0.55T
(2)
T = Periods
t
per
Output Period T - 400 ps T = Desired
Period
t
os
Output-to-Output Skew Rising Edges
Falling Edges
400
500
ps
t
r
, t
f
Rise/Fall Times (Slew Rate) 1.0 4.0 V/ns Series
Terminated
Transmission
Lines
t
EN
Enable Time ENABLE1
ENABLE2
5.0
4.0
ms
Cycles
t
DIS
Disable Time ENABLE1
ENABLE2
4.0
4.0
Cycles
A
osc
XTAL_IN to XTAL_OUT Oscillator Gain 6.0 dB
Phase Loop Phase Shift Modulo 360 + 30 Degrees
P1-P3P4-P6P7-P8

MPC905EF

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Manufacturer:
NXP / Freescale
Description:
Clock Buffer 2.5 3.3V 400MHz Clock Generator
Lifecycle:
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