LTC1871-7
25
18717fd
applicaTions inForMaTion
The maximum output voltage for a SEPIC converter is:
V
O(MAX)
= V
IN
+ V
D
( )
D
MAX
1 D
MAX
V
D
1
1 D
MAX
The maximum duty cycle of the LTC1871-7 is typically 92%.
SEPIC Converter: The Peak and Average
Input Currents
The control circuit in the LTC1871-7 is measuring the input
current (using a sense resistor in the MOSFET source),
so the output current needs to be reflected back to the
input in order to dimension the power MOSFET properly.
Based on the fact that, ideally, the output power is equal
to the input power, the maximum input current for a SEPIC
converter is:
I
IN(MAX)
= I
O(MAX)
D
MAX
1 D
MAX
The peak input current is :
I
IN(PEAK)
= 1+
χ
2
I
O(MAX)
D
MAX
1 D
MAX
The maximum duty cycle, D
MAX
, should be calculated at
minimum V
IN
.
The constant ‘
χ
’ represents the fraction of ripple current in
the inductor relative to its maximum value. For example, if
30% ripple current is chosen, then
χ
= 0.30 and the peak
current is 15% greater than the average.
It is worth noting here that SEPIC converters that operate
at high duty cycles (i.e., that develop a high output voltage
from a low input voltage) can have very high input currents,
relative to the output current. Be sure to check that the
maximum load current will not overload the input supply.
SEPIC Converter: Inductor Selection
For most SEPIC applications the equal inductor values
will fall in the range of 10µH to 100µH. Higher values will
reduce the input ripple voltage and reduce the core loss.
Lower inductor values are chosen to reduce physical size
and improve transient response.
Like the boost converter, the input current of the SEPIC
converter is calculated at full load current and minimum
input voltage. The peak inductor current can be significantly
higher than the output current, especially with smaller in-
ductors and lighter loads. The following formulas assume
CCM operation and calculate the maximum peak inductor
currents at minimum V
IN
:
I
L1(PEAK)
= 1+
χ
2
I
O(MAX)
V
O
+ V
D
V
IN(MIN)
I
L2(PEAK)
= 1+
χ
2
I
O(MAX)
V
IN(MIN)
+ V
D
V
IN(MIN)
The ripple current in the inductor is typically 20% to 40%
(i.e., a range of ‘
χ
’ from 0.20 to 0.40) of the maximum
average input current occurring at V
IN(MIN)
and I
O(MAX)
and
I
L1
= I
L2
. Expressing this ripple current as a function of
the output current results in the following equations for
calculating the inductor value:
L =
V
IN(MIN)
I
L
f
D
MAX
where
I
L
= χ I
O(MAX)
D
MAX
1 D
MAX
By making L1 = L2 and winding them on the same core,
the value of inductance in the equation above is replace
by 2L due to mutual inductance. Doing this maintains the
same ripple current and energy storage in the inductors. For
example, a Coiltronix CTX10-4 is a 10µH inductor with two
windings. With the windings in parallel, 10µH inductance
is obtained with a current rating of 4A (the number of
turns hasn’t changed, but the wire diameter has doubled).
Splitting the two windings creates two 10µH inductors
with a current rating of 2A each. Therefore, substituting
2L yields the following equation for coupled inductors:
L1= L2 =
V
IN(MIN)
2 I
L
f
D
MAX
Specify the maximum inductor current to safely handle
I
L(PK)
specified in the equation above. The saturation current
LTC1871-7
26
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rating for the inductor should be checked at the minimum
input voltage (which results in the highest inductor cur-
rent) and maximum output current.
SEPIC Converter: Power MOSFET Selection
Important parameters for the power MOSFET include the
drain-to-source breakdown voltage (BV
DSS
), the threshold
voltage (V
GS(TH)
), the on-resistance (R
DS(ON)
) versus gate-
to-source voltage, the gate-to-source and gate-to-drain
charges (Q
GS
and Q
GD
, respectively), the maximum drain
current (I
D(MAX)
) and the MOSFETs thermal resistances
(R
TH(JC)
and R
TH(JA)
).
The gate drive voltage is set by the 7V INTV
CC
low dropout
regulator. Consequently, 6V rated threshold MOSFETs are
required in most LTC1871-7 applications.
The maximum voltage that the MOSFET switch must
sustain during the off-time in a SEPIC converter is equal
to the sum of the input and output voltages (V
O
+ V
IN
).
As a result, careful attention must be paid to the BV
DSS
specifications for the MOSFETs relative to the maximum
actual switch voltage in the application. Many logic-level
devices are limited to 30V or less. Check the switching
waveforms directly across the drain and source terminals
of the power MOSFET to ensure the V
DS
remains below
the maximum rating for the device.
Sense Resistor Selection
During the MOSFETs on-time, the control circuit limits
the maximum voltage drop across the power MOSFET to
about 150mV (at low duty cycle). The peak inductor cur-
rent is therefore limited to 150mV/R
SENSE
. The relationship
between the maximum load current, duty cycle and the
sense resistor is:
R
SENSE
V
SENSE(MAX)
I
O(MAX)
1
1+
χ
2
1
V
O
+ V
D
V
IN(MIN)
+1
The V
SENSE(MAX)
term is typically 150mV at low duty
cycle and is reduced to about 100mV at a duty cycle of
92% due to slope compensation, as shown in Figure 11.
The constant ‘
χ
’ in the denominator represents the ripple
current in the inductors relative to their maximum current.
For example, if 30% ripple current is chosen, then
χ
= 0.30.
Calculating Power MOSFET Switching and Conduction
Losses and Junction Temperatures
In order to calculate the junction temperature of the
power MOSFET, the power dissipated by the device must
be known. This power dissipation is a function of the
duty cycle, the load current and the junction temperature
itself. As a result, some iterative calculation is normally
required to determine a reasonably accurate value. Since
the controller is using the MOSFET as both a switching
and a sensing element, care should be taken to ensure
that the converter is capable of delivering the required
load current over all operating conditions (load, line and
temperature) and for the worst-case specifications for
V
SENSE(MAX)
and the R
DS(ON)
of the MOSFET listed in the
manufacturers data sheet.
The power dissipated by the MOSFET in a SEPIC converter
is:
P
FET
= I
O(MAX)
D
1 D
2
R
DS(ON)
D ρ
T
+ k V
IN
+ V
O
( )
2
I
O(MAX)
D
1 D
C
RSS
f
The first term in the equation above represents the I
2
R
losses in the device and the second term, the switching
losses. The constant k = 1.7 is an empirical factor inversely
related to the gate drive current and has the dimension
of 1/current.
The ρ
T
term accounts for the temperature coefficient of
the R
DS(ON)
of the MOSFET, which is typically 0.4%/°C.
Figure
12 illustrates the variation of normalized R
DS(ON)
over temperature for a typical power MOSFET.
LTC1871-7
27
18717fd
applicaTions inForMaTion
From a known power dissipated in the power MOSFET, its
junction temperature can be obtained using the following
formula:
T
J
= T
A
+ P
FET
• R
TH(JA)
The R
TH(JA)
to be used in this equation normally includes
the R
TH(JC)
for the device plus the thermal resistance from
the board to the ambient temperature in the enclosure.
This value of T
J
can then be used to check the original
assumption for the junction temperature in the iterative
calculation process.
SEPIC Converter: Output Diode Selection
To maximize efficiency, a fast-switching diode with low
forward drop and low reverse leakage is desired. The output
diode in a SEPIC converter conducts current during the
switch off-time. The peak reverse voltage that the diode
must withstand is equal to V
IN(MAX)
+ V
O
. The average
forward current in normal operation is equal to the output
current, and the peak current is equal to:
I
D(PEAK)
= 1+
χ
2
I
O(MAX)
V
O
+ V
D
V
IN(MIN)
+ 1
The power dissipated by the diode is:
P
D
= I
O(MAX)
• V
D
and the diode junction temperature is:
T
J
= T
A
+ P
D
• R
TH(JA)
The R
TH(JA)
to be used in this equation normally includes
the R
TH(JC)
for the device plus the thermal resistance from
the board to the ambient temperature in the enclosure.
SEPIC Converter: Output Capacitor Selection
Because of the improved performance of todays electro-
lytic, tantalum and ceramic capacitors, engineers need
to consider the contributions of ESR (equivalent series
resistance), ESL (equivalent series inductance) and the
bulk capacitance when choosing the correct component
for a given output ripple voltage. The effects of these three
parameters (ESR, ESL, and bulk C) on the output voltage
ripple waveform are illustrated in Figure 21 for a typical
coupled-inductor SEPIC converter.
The choice of component(s) begins with the maximum
acceptable ripple voltage (expressed as a percentage of
the output voltage), and how this ripple should be divided
between the ESR step and the charging/discharging V.
For the purpose of simplicity we will choose 2% for the
maximum output ripple, to be divided equally between the
ESR step and the charging/discharging V. This percentage
ripple will change, depending on the requirements of the
application, and the equations provided below can easily
be modified.
For a 1% contribution to the total ripple voltage, the ESR
of the output capacitor can be determined using the fol-
lowing equation:
ESR
COUT
0.01 V
O
I
D(PEAK)
where:
I
D(PEAK)
= 1+
χ
2
I
O(MAX)
V
O
+ V
D
V
IN(MIN)
+ 1
For the bulk C component, which also contributes 1% to
the total ripple:
C
OUT
I
O(MAX)
0.01 V
O
f
For many designs it is possible to choose a single capacitor
type that satisfies both the ESR and bulk C requirements
for the design. In certain demanding applications, however,
the ripple voltage can be improved significantly by con-
necting two or more types of capacitors in parallel. For
example, using a low ESR ceramic capacitor can minimize
the ESR step, while an electrolytic or tantalum capacitor
can be used to supply the required bulk C.
Once the output capacitor ESR and bulk capacitance have
been determined, the overall ripple voltage waveform

LTC1871EMS-7#PBF

Mfr. #:
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Controllers No Rsense DC/DC Controller Boost, Flyback & SEPIC
Lifecycle:
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