MAX2140
Complete SDARS Receiver
_______________________________________________________________________________________ 9
Pin Description
PIN NAME FUNCTION
1, 4, 8,
12–15, 23,
26, 27, 30,
31, 40
VCC_FE0, VCC_FE1,
VCC_FE2, VCC_BE1,
VCC_BE2, VCC_BE3,
VINANT, VCC_XTAL,
VCC_D, VCC_A,
VCC_FE3, VCC_VCO,
VCC_BE4
Power Supplies. Bypass to ground with capacitors as close to the pins as possible.
2, 3 RFIN+, RFIN-
Differential RF Inputs. Accept RF input signal from the SDARS cabled antenna with a 50Ω to
100Ω balun.
5, 6 IFOUT+, IFOUT- Differential First IF Output. Connect an external SAW filter to the IF output.
7 RFAGC_C RF AGC Power-Detector Output. Set the RF AGC attack and decay response times.
9 AGCPWM
IF AGC Control Voltage Input. Input from the filtered PWM AGC control signal from the SDARS
channel-decoder IC.
10, 11 IFIN+, IFIN- Differential First IF Input
16 VOUTANT
Overcurrent-Protected Unregulated DC Supply Output. Provides DC power supply to the
antenna module.
17, 19, 37,
39
IF2IO-, IF2IO+,
IF2QO+, IF2QO-
Differential Baseband DC Blocking Outputs.
IF2IO- = Inverting in-phase baseband output. AC couple to pin 18.
IF2IO+ = Noninverting in-phase baseband output. AC couple to pin 20.
IF2QO+ = Noninverting quadrature baseband output. AC couple to pin 36.
IF2QO- = Inverting quadrature baseband output. AC couple to pin 38.
18, 20, 36,
38
IF2II-, IF2II+, IF2QI+,
IF2QI-
Differential Baseband DC Blocking Inputs.
IF2II- = Inverting in-phase baseband input. AC couple to pin 16.
IF2II+ = Noninverting in-phase baseband input. AC couple to pin 19.
IF2QI+ = Noninverting quadrature baseband input. AC couple to pin 37.
IF2QI- = Inverting quadrature baseband input. AC couple to pin 39.
21, 22, 34,
35
IOUT-, IOUT+,
QOUT+, QOUT-
Differential I/Q Baseband Outputs.
IOUT- = Inverting in-phase baseband output.
IOUT+ = Noninverting in-phase baseband output.
QOUT+ = Noninverting quadrature baseband output.
QOUT- = Inverting quadrature baseband output.
24 XTAL Crystal Reference Input
25 REFOUT Buffered System Clock Output. Provides clock signal to the SDARS channel-decoder IC.
28 LOCK Digital Logic Output to the System Controller. Indicates the lock status of the internal PLL.
29 CPOUT VCO Charge-Pump Output
32 VCCREG Regulated Supply Voltage for the VCO
33 VTUNE High-Impedance VCO Tuning Input
41, 42 I
2
CA2, I
2
CA1 I
2
C Input Signals. Define the MAX2140 I
2
C device address.
43, 44 SCL, SDA I
2
C-Compatible Programming Input. Connect to an I
2
C-compatible bus.
— Exposed Pad Exposed Paddle. Connect to ground.
