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MC74AC573DTR2

P1-P3P4-P6P7-P9P10-P10
© Semiconductor Components Industries, LLC, 2015
March, 2015 − Rev. 8
1 Publication Order Number:
MC74AC573/D
MC74AC573, MC74ACT573
Octal Buffer/Line Driver
with 3-State Outputs
The MC74AC573/74ACT573 is a high−speed octal latch with
buffered common Latch Enable (LE) and buffered common Output
Enable (OE
) inputs.
The MC74AC573/74ACT573 is functionally identical to the
MC74AC373/74ACT373 but has inputs and outputs on opposite sides.
Features
• Inputs and Outputs on Opposite Sides of Package Allowing Easy
Interface with Microprocessors
• Useful as Input or Output Port for Microprocessors
• Functionally Identical to MC74AC373/74ACT373
• 3−State Outputs for Bus Interfacing
• Outputs Source/Sink 24 mA
• ′ACT573 Has TTL Compatible Inputs
• These are Pb−Free Devices
Figure 1. Pinout 20−Lead Packages Conductors
(Top View)
1920 18 17 16 15 14
21 34567
V
CC
13
8
12
9
11
10
O
0
O
1
O
2
O
3
O
4
O
5
O
6
O
7
LE
OE
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
GND
PIN ASSIGNMENT
PIN FUNCTION
D
0
−D
7
Data Inputs
LE Latch Enable Input
OE 3−State Output Enable Input
O
0
−O
7
3−State Latch Outputs
Figure 2. Logic Symbol
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
LE
O
1
O
2
O
3
O
4
O
5
O
6
O
7
OE
O
0
1
20
1
20
SO−20
DW SUFFIX
CASE 751D
TSSOP−20
DT SUFFIX
CASE 948E
www.onsemi.com
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
ORDERING INFORMATION
xxx573
AWLYYWWG
xxx
573
ALYW G
G
xxx = AC or ACT
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G or G = Pb−Free Package
(Note: Microdot may be in either location)
MARKING
DIAGRAM
MC74AC573, MC74ACT573
www.onsemi.com
2
TRUTH TABLE
Inputs Outputs
OE LE D
n
O
n
L H H H
L H L L
L L X O
0
H X X Z
H = HIGH Voltage Level
L = LOW Voltage Level
Z = High Impedance
X = Immaterial
O
0
= Previous O
0
before LOW−to−HIGH Transition of Clock
Functional Description
The MC74AC573/74ACT574 contains eight D−type
latches with 3−state output buffers. When the Latch Enable
(LE) input is HIGH, data on the D
n
inputs enters the latches.
In this condition the latches are transparent, i.e., a latch
output will change state each time its D input changes. When
LE is LOW the latches store the information that was present
on the D inputs a setup time preceding the HIGH−to−LOW
transition of LE. The 3−state buffers are controlled by the
Output Enable (OE
) input. When OE is LOW, the buffers are
enabled. When OE
is HIGH the buffers are in the high
impedance mode but this does not interfere with entering
new data into the latches.
Figure 3. Logic Diagram
D
LE
Q
D
LE
Q
D
LE
Q
D
LE
Q
D
LE
Q
D
LE
Q
D
LE
Q
D
LE
Q
D
1
D
2
D
3
D
4
D
5
D
6
D
7
LE
OE
O
0
O
1
O
2
O
3
O
4
O
5
O
6
O
7
D
0
NOTE: That this diagram is provided only for the understanding of logic
operations and should not be used to estimate propagation delays.
MC74AC573, MC74ACT573
www.onsemi.com
3
MAXIMUM RATINGS
Symbol Parameter Value Unit
V
CC
DC Supply Voltage (Referenced to GND) −0.5 to +7.0 V
V
IN
DC Input Voltage (Referenced to GND) −0.5 to V
CC
+0.5 V
V
OUT
DC Output Voltage (Referenced to GND) (Note 1) −0.5 to V
CC
+0.5 V
I
IK
DC Input Diode Current ±20 mA
I
OK
DC Output Diode Current ±50 mA
I
OUT
DC Output Sink/Source Current ±50 mA
I
CC
DC Supply Current, per Output Pin ±50 mA
I
GND
DC Ground Current, per Output Pin ±100 mA
T
STG
Storage Temperature Range *65 to )150
_C
T
L
Lead temperature, 1 mm from Case for 10 Seconds 260
_C
T
J
Junction Temperature Under Bias 140
_C
q
JA
Thermal Resistance (Note 2) SOIC
TSSOP
65.8
110.7
_C/W
MSL Moisture Sensitivity Level 1
F
R
Flammability Rating Oxygen Index: 30% − 35% UL 94 V−0 @ 0.125 in
V
ESD
ESD Withstand Voltage Human Body Model (Note 3)
Machine Model (Note 4)
Charged Device Model (Note 5)
> 2000
> 200
> 1000
V
I
Latchup
Latchup Performance Above V
CC
and Below GND at 85_C (Note 6)
±100 mA
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. I
OUT
absolute maximum rating must be observed.
2. The package thermal impedance is calculated in accordance with JESD 51−7.
3. Tested to EIA/JESD22−A114−A.
4. Tested to EIA/JESD22−A115−A.
5. Tested to JESD22−C101−A.
6. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Typ Max Unit
V
CC
Supply Voltage
′AC 2.0 5.0 6.0
V
′ACT 4.5 5.0 5.5
V
IN
, V
OUT
DC Input Voltage, Output Voltage (Ref. to GND) 0 − V
CC
V
t
r
, t
f
Input Rise and Fall Time (Note 1)
′AC Devices except Schmitt Inputs
V
CC
@ 3.0 V − 150 −
V
CC
@ 4.5 V − 40 − ns/V
V
CC
@ 5.5 V − 25 −
t
r
, t
f
Input Rise and Fall Time (Note 2)
′ACT Devices except Schmitt Inputs
V
CC
@ 4.5 V − 10 −
ns/V
V
CC
@ 5.5 V − 8.0 −
T
A
Operating Ambient Temperature Range −40 25 85 °C
I
OH
Output Current − High − − −24 mA
I
OL
Output Current − Low − − 24 mA
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
1. V
IN
from 30% to 70% V
CC
; see individual Data Sheets for devices that differ from the typical input rise and fall times.
2. V
IN
from 0.8 V to 2.0 V; see individual Data Sheets for devices that differ from the typical input rise and fall times.
P1-P3P4-P6P7-P9P10-P10

MC74AC573DTR2

Mfr. #:
Buy MC74AC573DTR2
Manufacturer:
ON Semiconductor
Description:
IC LATCH OCTAL 20-TSSOP
Lifecycle:
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