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SST39VF1682-70-4I-B3KE

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P34
©2011 Silicon Storage Technology, Inc. DS25040A 05/11
16
16 Mbit Multi-Purpose Flash Plus
SST39VF1681 / SST39VF1682
Data Sheet
A
Microchip Technology Company
Table 17:Program/Erase Cycle Timing Parameters
Symbol Parameter Min Max Units
T
BP
Byte-Program Time 10 µs
T
AS
Address Setup Time 0 ns
T
AH
Address Hold Time 30 ns
T
CS
WE# and CE# Setup Time 0 ns
T
CH
WE# and CE# Hold Time 0 ns
T
OES
OE# High Setup Time 0 ns
T
OEH
OE# High Hold Time 10 ns
T
CP
CE# Pulse Width 40 ns
T
WP
WE# Pulse Width 40 ns
T
WPH
1
WE# Pulse Width High 30 ns
T
CPH
1
CE# Pulse Width High 30 ns
T
DS
Data Setup Time 30 ns
T
DH
1
Data Hold Time 0 ns
T
IDA
1
Software ID Access and Exit Time 150 ns
T
SE
Sector-Erase 25 ms
T
BE
Block-Erase 25 ms
T
SCE
Chip-Erase 50 ms
T17.0 25040
1. This parameter is measured only for initial qualification and after a design or process change that could affect this
parameter.
©2011 Silicon Storage Technology, Inc. DS25040A 05/11
17
16 Mbit Multi-Purpose Flash Plus
SST39VF1681 / SST39VF1682
Data Sheet
A
Microchip Technology Company
Figure 4: Read Cycle Timing Diagram
Figure 5: WE# Controlled Program Cycle Timing Diagram
1243 F02.0
ADDRESS A
MS-0
DQ
15-0
WE#
OE#
CE#
T
CE
T
RC
T
AA
T
OE
T
OLZ
V
IH
HIGH-Z
T
CLZ
T
OH
T
CHZ
HIGH-Z
DATA VALIDDATA VALID
T
OHZ
Note: A
MS
= Most Significant Address
A
MS
=A
20
for SST39VF168x
1243 F03.2
ADDRESS A
MS-0
DQ
7-0
T
DH
T
WPH
T
DS
T
WP
T
AH
T
AS
T
CH
T
CS
CE#
SW0 SW1 SW2
AAA AAA555 ADDR
AA 55 A0 DATA
INTERNAL PROGRAM OPERATION STARTS
BYTE
(ADDR/DATA)
OE#
WE#
T
BP
Note: A
MS
= Most Significant Address
A
MS
=A
20
for SST39VF168x
WP# must be held in proper logic state (V
IL
or V
IH
) 1 µs prior to and 1 µs after the command sequence.
X can be V
IL
or V
IH,
but no other value.
©2011 Silicon Storage Technology, Inc. DS25040A 05/11
18
16 Mbit Multi-Purpose Flash Plus
SST39VF1681 / SST39VF1682
Data Sheet
A
Microchip Technology Company
Figure 6: CE# Controlled Program Cycle Timing Diagram
Figure 7: Data# Polling Timing Diagram
1243 F04.2
ADDRESS A
MS-0
DQ
7-0
T
DH
T
CPH
T
DS
T
CP
T
AH
T
AS
T
CH
T
CS
WE#
SW0 SW1 SW2
AAA AAA555 ADDR
AA 55 A0 DATA
INTERNAL PROGRAM OPERATION STARTS
BYTE
(ADDR/DATA)
OE#
CE#
T
BP
Note: A
MS
= Most Significant Address
A
MS
=A
20
for SST39VF168x
WP# must be held in proper logic state (V
IL
or V
IH
) 1 µs prior to and 1 µs after the command sequence.
X can be V
IL
or V
IH,
but no other value.
1243 F05.1
ADDRESS A
MS-0
DQ
7
DATA DATA # DATA # DATA
WE#
OE#
CE#
T
OEH
T
OE
T
CE
T
OES
Note: A
MS
= Most Significant Address
A
MS
=A
20
for SST39VF168x
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P34

SST39VF1682-70-4I-B3KE

Mfr. #:
Buy SST39VF1682-70-4I-B3KE
Manufacturer:
Microchip Technology
Description:
NOR Flash 2.7 to 3.6V 16Mbit Multi-Purpose Flash
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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