NCV8504 Series
http://onsemi.com
9
CIRCUIT DESCRIPTION
REGULATOR CONTROL FUNCTIONS
The NCV8504 contains the microprocessor compatible
control function RESET
(Figure 13).
Figure 13. Reset and Delay Circuit Wave Forms
V
IN
V
OUT
RESET
DELAY
(V
DT
)
Threshold
DELAY
Threshold
RESET
T
d
T
d
RESET Function
A RESET signal (low voltage) is generated as the IC
powers up until V
OUT
is within 1.5% of the regulated output
voltage, or when V
OUT
drops out of regulation,and is lower
than 4.0% below the regulated output voltage. Hysteresis is
included in the function to minimize oscillations.
The RESET
output is an open collector NPN transistor,
controlled by a low voltage detection circuit. The circuit is
functionally independent of the rest of the IC thereby
guaranteeing that the RESET
signal is valid for V
OUT
as low
as 1.0 V.
Adjustable Reset Function
The reset threshold can be made lower by connecting an
external resistor divider to the R
ADJ
lead from the V
OUT
lead, as displayed in Figure 14. This lead is grounded to
select the default value of 4.6 V (on the 5.0 V option).
Figure 14. Adjustable RESET
R
ADJ
to μP and
System
Power
R
RST
V
OUT
C
OUT
RESET
C
DELAY
DELAY
NCV8504
to μP and
RESET
Port
V
R(ADJ)
DELAY Function
The reset delay circuit provides a programmable (by
external capacitor) delay on the RESET
output lead.
The DELAY lead provides source current (typically 4.0 μA)
to the external DELAY capacitor during the following
proceedings:
1. During Power Up (once the regulation threshold
has been verified).
2. After a reset event has occurred and the device is
back in regulation. The DELAY capacitor is
discharged when the regulation (RESET
threshold)
has been violated. This is a latched incident. The
capacitor will fully discharge and wait for the
device to regulate before going through the delay
time event again.
FLAG/Monitor Comparator
A general use comparator is included whose positive input
terminal is tied to the on−chip bandgap voltage reference.
This provides a very temperature stable referenced
comparator with versatile use in any system. The trip point
can be programmed externally using a resistor divider to the
input monitor (MON) (Figure 15). The typical threshold is
1.29 V on the MON pin.
Figure 15. Flag/Monitor Function
V
BAT
V
IN
MON
V
OUT
C
OUT
V
CC
I/O
RESET
μP
FLAG
RESET
GND
DELAY
NCV8504
R
ADJ
V
MON
Voltage Adjust
Figure 16 shows the device setup for a user configurable
output voltage. The feedback to the V
ADJ
pin is taken from
a voltage divider referenced to the output voltage. The loop
is balanced around the Unity Gain threshold (1.30 V
typical).
Figure 16. Adjustable Output
Voltage
V
OUT
V
ADJ
NCV8504
15 k
5.1 k
C
OUT
≈5.0 V
1.28 V
