Data Sheet ADF4154
Rev. C | Page 9 of 24
CIRCUIT DESCRIPTION
REFERENCE INPUT SECTION
The reference input stage is shown in Figure 14. While the
device is operating, usually SW1 and SW2 are closed switches
and SW3 is open. When a power-down is initiated, SW3 is
closed and SW1 and SW2 are opened. This ensures that the
REF
IN
pin is not loaded while the device is powered down.
BUFFER
TO R COUNTER
REF
IN
100kΩ
NC
SW2
SW3
NO
NC
SW1
POWER-DOWN
CONTROL
04833-027
Figure 14. Reference Input Stage
RF INPUT STAGE
The RF input stage is shown in Figure 15. It is followed by a
two-stage limiting amplifier to generate the current mode logic
(CML) clock levels needed for the prescaler.
BIAS
GENERATOR
1.6V
AGND
AV
DD
2kΩ 2kΩ
RF
IN
B
RF
IN
A
04833-015
Figure 15. RF Input Stage
RF INT DIVIDER
The RF INT CMOS counter allows a division ratio in the PLL
feedback counter. Division ratios from 31 to 511 are allowed.
THIRD ORDER
FRACTIONAL
INTERPOLATOR
FRAC
VALUE
MOD
REG
INT
REG
RF N-DIVIDER
N = INT + FRAC/MOD
FROM RF
INPUT STAGE
TO PFD
N COUNTER
04833-016
Figure 16. A and B Counters
INT, FRAC, MOD, AND R RELATIONSHIP
The INT, FRAC, and MOD values, in conjunction with the
R-counter, enable generating output frequencies that are spaced by
fractions of the PFD. See the RF Synthesizer: A Worked Example
section for more information. The RF VCO frequency (RF
OUT
)
equation is
PFD
OUT
(1)
where RF
OUT
is the output frequency of the external voltage-
controlled oscillator (VCO).
RDREFF
INPFD
1
(2)
where:
REF
IN
is the reference input frequency.
D is the REF
IN
doubler bit.
R is the preset divide ratio of binary 4-bit programmable
reference counter (1 to 15).
INT is the preset divide ratio of binary 9-bit counter (31 to 511).
MOD is the preset modulus ratio of binary 12-bit program-
mable FRAC counter (2 to 4095).
FRAC is the preset fractional ratio of binary 12-bit
programmable FRAC counter (0 to MOD-1).
R-COUNTER
The 4-bit R-counter allows the input reference frequency
(REF
IN
) to be divided down to produce the reference clock to
the PFD. Division ratios from 1 to 15 are allowed.
PHASE FREQUENCY DETECTOR (PFD) AND
CHARGE PUMP
The PFD takes inputs from the R-counter and N-counter and
produces an output proportional to the phase and frequency
difference between them. Figure 17 is a simplified schematic.
The PFD includes a fixed delay element that sets the width of
the antibacklash pulse, which is typically 3 ns. This pulse
ensures that there is no dead zone in the PFD transfer function
and gives a consistent reference spur level.
U3
CLR2
Q2D2
U2
DOWN
UP
HI
HI
CP
–IN
+IN
CHARGE
PUMP
DELAY
CLR1
Q1D1
U1
04833-017
Figure 17. PFD Simplified Schematic
