PCA9621 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 1 — 9 March 2011 7 of 18
NXP Semiconductors
PCA9621
65 mA 8-bit 2-wire bus output port
10. Characteristics
Table 4. Characteristics
T
amb
=
−
40
°
C to +85
°
C; voltages are specified with respect to ground (V
SS
); V
DD
= 5.5 V unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Power supply
V
DD
supply voltage operating 2.7 - 5.5 V
I
DD
supply current quiescent; V
I
(RESET pin) = 0 V;
V
DD
=5.5V
--1μA
I
2
C-bus ports (SCL, SDA)
V
I2C-bus
I
2
C-bus voltage SDA, SCL V
SS
− 0.3 - V
DD
+0.3 V
V
IL
LOW-level input voltage V
DD
=2.7V
[1]
--0.4V
V
DD
=5.5V
[1]
--0.5V
V
IH
HIGH-level input voltage V
DD
=2.7V
[1]
1.2 - - V
V
DD
=5.5V
[1]
2.0 - - V
I
LI
input leakage current pin at V
DD
or V
SS
−1-+1μA
V
OL
LOW-level output voltage I
OL
=30mA; V
DD
= 2.7 V - 260 450 mV
I
OL
=30mA; V
DD
= 5.5 V - 140 275 mV
Open-drain output ports (P0 to P7)
I
O(sink)
output sink current LOW-level; port enabled 65 - - mA
V
OL
LOW-level output voltage I
OL
= 65 mA - 440 725 mV
I
OL
=100μA-1-mV
RESET
V
IH
HIGH-level input voltage V
DD
= 2.7 V 2.0 - - V
V
DD
= 5.5 V 4.8 - - V
V
IL
LOW-level input voltage V
DD
= 2.7 V - - 650 mV
V
DD
= 5.5 V - - 900 mV
V
hys
hysteresis voltage V
DD
= 2.7 V 100 - - mV
V
DD
= 5.5 V 200 - - mV
I
LI
input leakage current pin at V
DD
or V
SS
−1-+1μA
t
w(rst)L
LOW-level reset time V
I
<V
IL
[2]
-25-ns
t
rst
reset time RESET pin; from V
I
> V
IH
- 250 500 ns
t
POR
power-on reset pulse time RESET pin; from V
I
> V
IH
- 250 500 ns
Address pins (A0, A1, A2)
V
IH
HIGH-level input voltage V
DD
= 2.7 V 1.7 - - V
V
DD
= 5.5 V 3.5 - - V
V
IL
LOW-level input voltage V
DD
= 2.7 V - - 0.7 V
V
DD
= 5.5 V - - 1.5 V
I
LI
input leakage current pin at V
DD
or V
SS
−1-+1μA
Timing characteristics
t
f
fall time of both SDA and
SCL signals
R
PU
= 200 Ω; measured from
70 % V
DD
to 30 % V
DD
-16-ns
t
v(Q)
data output valid time
[3]
- - 500 ns
