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PCA9621PW,118

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18
PCA9621 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 1 — 9 March 2011 4 of 18
NXP Semiconductors
PCA9621
65 mA 8-bit 2-wire bus output port
7. Functional description
Refer to Figure 1 “Block diagram of PCA9621”.
7.1 V
DD
, V
SS
— DC supply pins
The power supply voltage for the PCA9621 may be any voltage in the range 2.7 V to
5.5 V. All other I/Os are clamped to V
DD
and V
SS
through ESD protection diodes.
7.2 SCL, SDA — 2-wire bus interface
The state of the output ports is determined by the Control register, which is set and read
via a 2-wire bus interface using I
2
C-bus style signalling. The interface is Fast-mode Plus
(Fm+) I
2
C-bus compatible, though the ports contain ESD protection diodes to the positive
and negative supplies. Consequently, V
I2C-bus
(voltage at SCL and SDA) must remain
within the V
DD
and V
SS
supply levels.
7.3 P0 to P7 — output ports
There are eight open-drain output ports whose state is determined by the Control register.
Programming a ‘1’ or HIGH to the relevant register bit will turn on the corresponding port,
resulting at a LOW or ‘0’ at the port. In the case of LED driving, this would result in the
LED turning ON.
Programming a ‘0’ or LOW in the register turns off the open-drain port, placing it in a
high-impedance mode.
The ports are protected by ESD diodes to the supplies so they must not be driven above
the V
DD
or below the V
SS
levels.
7.4 RESET — reset IC to default state
The active LOW RESET input is used to disable the buffer and reset it to its default state.
The RESET
signal will clear the contents of the Control register, turning off all output
ports, and resetting the state of the I
2
C-bus slave transceiver block.
7.5 Power-On Reset (POR)
During power-on, the PCA9621 is internally held in the reset condition for a maximum of
t
rst
= 500 ns. The default condition after reset is for the Control register to be erased
(all zeros), resulting in all output ports being off (high-impedance).
PCA9621 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 1 — 9 March 2011 5 of 18
NXP Semiconductors
PCA9621
65 mA 8-bit 2-wire bus output port
7.6 A0, A1, A2 — address lines
The slave address of the PCA9621 is shown in Figure 4. The address pins (A2, A1, A0)
must be driven to a HIGH or LOW level—they are not internally pulled to a default state.
The read/write bit must be set LOW to enable a write to the Control register, or HIGH to
read from the Control register.
7.7 Control register
The Control register of the PCA9621 is shown in Figure 5. Each of the four output ports
can be activated independently by setting the appropriate bit in the Control register.
A LOW or ‘zero’ bit indicates that the respective channel (P7 to P0) is disabled
(high-impedance). The default reset condition of the register is all zeros, all ports
high-impedance. A HIGH or ‘one’ bit indicates the respective channel is active (sinking).
Example: Programming C1h (1100 0001b) into the Control register results in ports P0, P6
and P7 being ON (sinking) and the remaining ports being OFF (high-impedance).
Fig 4. Slave address
002aaf38
3
1 1 0 0 A2 A1 A0 R/W
fixed externally
selectable
read = 1
write = 0
1 = ON (sinking)
0 = OFF (high-impedance)
Fig 5. Control register
002aaf3
84
P7 P6 P5 P4 P3 P2 P1 P0MSB LSB
PCA9621 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 1 — 9 March 2011 6 of 18
NXP Semiconductors
PCA9621
65 mA 8-bit 2-wire bus output port
8. Bus transaction
A typical I
2
C-bus write transaction to the PCA9621 is shown in Figure 6. During a write
transaction, the output ports (P0 to P7) of the PCA9621 are updated upon receipt of the
STOP condition.
A typical read transaction is shown in Figure 7.
9. Limiting values
[1] Voltages are specified with respect to pin 8 (V
SS
).
[2] 100 mA for one pin only in the group P0 to P3, and one pin only in the group P4 to P7. Otherwise 70 mA maximum, any pin.
Fig 6. PCA9621 write transaction to Control register
Fig 7. PCA9621 read transaction from Control register
002aaf38
5
S 1 1 0 0 A2 A1 A0
slave address
0 A P7 P6 P5 P4 P3 P2 P1 P0 A P
Control register
START
condition
R/W acknowledge
from slave
acknowledge
from slave
STOP
condition
002aaf38
6
S 1 1 0 0 A2 A1 A0
slave address
1 A P7 P6 P5 P4 P3 P2 P1 P0 NA P
Control register
START
condition
R/W acknowledge
from slave
not acknowledge
from master
STOP
condition
Table 3. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
V
DD
supply voltage
[1]
−0.3 +7 V
V
n
voltage on any other pin
[1]
V
SS
− 0.5 V
DD
+0.5 V
I
I
input current output ports (P0 to P7)
[2]
-100mA
SDA, SCL pins - 40 mA
address pins A0 to A2; RESET
pin - 20 mA
I
SS
ground supply current - 550 mA
P
tot
total power dissipation - 300 mW
T
stg
storage temperature −55 +125 °C
T
amb
ambient temperature operating −40 +85 °C
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18

PCA9621PW,118

Mfr. #:
Buy PCA9621PW,118
Manufacturer:
NXP Semiconductors
Description:
IC BUS PORT 8BIT 65MA 16TSSOP
Lifecycle:
New from this manufacturer.
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