Serial-Data Output
The serial-data output, DOUT, is the internal shift regis-
ter’s output. DOUT allows for daisy chaining of devices
and data readback. The MAX5154/MAX5155 can be
programmed to shift data out of DOUT on SCLK’s
falling edge (Mode 0) or on the rising edge (Mode 1).
Mode 0 provides a lag of 16 clock cycles, which main-
tains compatibility with SPI/QSPI and Microwire inter-
faces. In Mode 1, the output data lags 15.5 clock
cycles. On power-up, the device defaults to Mode 0.
User-Programmable Logic Output (UPO)
UPO allows an external device to be controlled through
the serial interface (Table 1), thereby reducing the
number of microcontroller I/O pins required. On power-
up, UPO is low.
Power-Down Lockout Input (
PPDDLL
)
The power-down lockout pin (PDL) disables software
shutdown when low. When in shutdown, transitioning
PDL from high to low wakes up the part with the output
set to the state prior to shutdown. PDL can also be
used to asynchronously wake up the device.
Daisy Chaining Devices
Any number of MAX5154/MAX5155s can be daisy
chained by connecting the DOUT pin of one device to
the DIN pin of the following device in the chain (Figure 7).
Since the MAX5154/MAX5155’s DOUT pin has an inter-
nal active pull-up, the DOUT sink/source capability
determines the time required to discharge/charge a
capacitive load. Refer to the digital output V
OH
and V
OL
specifications in the
Electrical Characteristics
.
Figure 8 shows an alternate method of connecting sev-
eral MAX5154/MAX5155s. In this configuration, the
data bus is common to all devices; data is not shifted
through a daisy chain. More I/O lines are required in
this configuration because a dedicated chip-select
input (CS) is required for each IC.
__________Applications Information
Unipolar Output
Figure 9 shows the MAX5154/MAX5155 configured for
unipolar, rail-to-rail operation with a gain of +2V/V. The
MAX5154 can produce a 0V to 4.096V output with
2.048V reference (Figure 9), while the MAX5155 can
produce a range of 0V to 2.5V with a 1.25V reference.
Table 2 lists the unipolar output codes. An offset to the
output can be achieved by connecting a voltage to
OS_, as shown in Figure 10. By applying V
OS
_ = -1V,
the output values will range between 1V and (1V +
V
REF
x 2).
MAX5154/MAX5155
Low-Power, Dual, 12-Bit Voltage-Output DACs
with Serial Interface
Table 2. Unipolar Code Table (Gain = +2)
MAX5154
MAX5155
DAC_
GAIN = +2V/V
REF_
OUT_
OS_
DGNDAGND
+5V/+3V
V
DD
R
R
Figure 9. Unipolar Output Circuit (Rail-to-Rail)
MAX5154
MAX5155
DAC _
AGND DGND
REF_
OUT_
OS_
V
OS
+5V/+3V
V
DD
R
R
______________________________________________________________________________________ 13
ANALOG OUTPUT
1111 1111 1111 (0)
1000 0000 0001 (0)
DAC CONTENTS
MSB LSB
1000 0000 0000 (0)
0111 1111 1111 (0)
0000 0000 0000 (0) 0V
0000 0000 0001 (0)
+V
4095
4096
2
REF
x
+V
2049
4096
REF
x 2
+V
2048
4096
V
REF REF
= x 2
+V
2047
4096
REF
x 2
+V
1
4096
REF
x 2
Figure 10. Setting OS_ for Output Offset
Note: ( ) are for the sub bit.
MAX5154/MAX5155
Bipolar Output
The MAX5154/MAX5155 can be configured for a bipo-
lar output, as shown in Figure 11. The output voltage is
given by the equation (OS_ = AGND):
V
OUT
= V
REF
[((2 x NB) / 4096) - 1]
where NB represents the numeric value of the DAC’s
binary input code. Table 3 shows digital codes and the
corresponding output voltage for Figure 11’s circuit.
Using an AC Reference
In applications where the reference has an AC signal
component, the MAX5154/MAX5155 have multiplying
capabilities within the reference input voltage range
specifications. Figure 12 shows a technique for apply-
ing a sinusoidal input to REF_, where the AC signal is
offset before being applied to the reference input.
Harmonic Distortion and Noise
The total harmonic distortion plus noise (THD+N) is typ-
ically less than -78dB at full scale with a 1Vp-p input
swing at 5kHz. The typical -3dB frequency is 300kHz
for both devices, as shown in the
Typical Operating
Characteristics.
Digital Calibration and
Threshold Selection
Figure 13 shows the MAX5154/MAX5155 in a digital
calibration application. With a bright light value applied
to the photodiode (on), the DAC is digitally ramped until
Low-Power, Dual, 12-Bit Voltage-Output DACs
with Serial Interface
14 ______________________________________________________________________________________
Table 3. Bipolar Code Table
ANALOG OUTPUT
1111 1111 1 111 (0)
1000 0000 0 001 (0)
DAC CONTENTS
MSB LSB
1000 0000 0 000 (0) 0V
0111 1111 1 111 (0)
0000 0000 0 000 (0)
0000 0000 0 001 (0)
+V
2047
2048
REF
+V
1
2048
REF
-V
1
2048
REF
-V
2047
2048
REF
-V
2048
2048
- V
REF REF
=
AGNDDGND
R
R
MAX5154
MAX5155
DAC _
REF_
OS_
OUT_
10k 10k
10k
10k
V-
V+
V
DD
V
OUT
+5V/+3V
Figure 11. Bipolar Output Circuit
DAC_
OUT_
MAX5154
MAX5155
10k
26k
OS_
REF
R
R
V
DD
DGNDAGND
+5V/
+3V
AC
REFERENCE
INPUT
500mVp-p
MAX495
+5V/+3V
Figure 12. AC Reference Input Circuit
AGND
DIN
µP
DGND
MAX5154
MAX5155
DAC _
REF_
OS_
OUT_
R
R
V-
V+
PHOTODIODE
V+
V
DD
V
OUT
R
PULLDOWN
+5V/+3V
Figure 13. Digital Calibration
Note: ( ) are for the sub bit.
it trips the comparator. The microprocessor (µP) stores
this “high” calibration value. Repeat the process with a
dim light (off) to obtain the dark current calibration.
The µP then programs the DAC to set an output voltage
at the midpoint of the two calibrated values.
Applications include tachometers, motion sensing,
automatic readers, and liquid clarity analysis.
Digital Control of Gain and Offset
The two DACs can be used to control the offset and
gain for curve-fitting nonlinear functions, such as trans-
ducer linearization or analog compression/expansion
applications. The input signal is used as the reference
for the gain-adjust DAC, whose output is summed with
the output from the offset-adjust DAC. The relative
weight of each DAC output is adjusted by R1, R2, R3,
and R4 (Figure 14).
Power-Supply Considerations
On power-up, the input and DAC registers clear (set to
zero code). For rated performance, V
REF_
should be at
least 1.4V below V
DD
. Bypass the power supply with a
4.7µF capacitor in parallel with a 0.1µF capacitor to
AGND. Minimize lead lengths to reduce lead inductance.
Grounding and Layout Considerations
Digital and AC transient signals on AGND can create
noise at the output. Connect AGND to the highest quality
ground available. Use proper grounding techniques,
such as a multilayer board with a low-inductance ground
plane. Carefully lay out the traces between channels to
reduce AC cross-coupling and crosstalk. Wire-wrapped
boards and sockets are not recommended. If noise
becomes an issue, shielding may be required.
MAX5154/MAX5155
Low-Power, Dual, 12-Bit Voltage-Output DACs
with Serial Interface
______________________________________________________________________________________ 15
AGND DGND
MAX5154
MAX5155
DACA
V
DD
REFA
V
IN
V
REF
CS
SCLK
DIN
REFB
R1
R3
R
R
R
R
R4
R2
OUTB
OSB
OUTA
OSA
V
OUT
DACB
INPUT
REG A
INPUT
REG B
DAC
REG A
DAC
REG B
– OFFSET
[ ]
V
OUT
=
=
GAIN
[ ]
2NA
4096
NA IS THE NUMERIC VALUE OF THE INPUT CODE FOR DACA.
NB IS THE NUMERIC VALUE OF THE INPUT CODE FOR DACB.
R2
R1+R2
R4
R3
2NB
4096
R4
R3
(
V
IN
)(
)(
1+
)
(
V
REF
)(
)
[ ] [ ]
SHIFT
REGISTER
Figure 14. Digital Control of Gain and Offset

MAX5154BCEE+

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Digital to Analog Converters - DAC 12-Bit 2Ch Precision DAC
Lifecycle:
New from this manufacturer.
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