Philips Semiconductors Product specification
74ALVT162821
2.5V/3.3V 20-bit bus-interface D-type flip-flop;
positive-edge trigger with 30 termination resistors (3-State)
2
1998 Oct 02 853-2041 20127
FEATURES
• Outputs include series resistance of 30 making external
termination resistors unnecessary
• 20-bit positive-edge triggered register
• 5V I/O Compatible
• Multiple V
CC
and GND pins minimize switching noise
• Live insertion/extraction permitted
• Power-up reset
• Power-up 3-State
• Output capability +12mA/-12mA
• Latch-up protection exceeds 500mA per Jedec Std 17
• ESD protection exceeds 2000V per MIL STD 883 Method 3015
and 200V per Machine Model
• Bus hold data inputs eliminate the need for external pull-up
resistors to hold unused inputs
DESCRIPTION
The 74ALVT162821 high-performance BiCMOS device combines
low static and dynamic power dissipation with high speed and high
output drive. It is designed for V
CC
operation at 2.5V or 3.3V with I/O
compatibility to 5V.
The 74ALVT162821 has two 10-bit, edge triggered registers, with
each register coupled to a 3-State output buffer. The two sections of
each register are controlled independently by the clock (nCP) and
Output Enable (nOE
) control gates.
Each register is fully edge triggered. The state of each D input, one
set-up time before the Low-to-High clock transition, is transferred to
the corresponding flip-flop’s Q output.
The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors.
The active Low Output Enable (nOE
) controls all ten 3-State buffers
independent of the register operation. When nOE
is Low, the data in
the register appears at the outputs. When nOE
is High, the outputs
are in high impedance “off” state, which means they will neither drive
nor load the bus.
The 74ALVT162821 is designed with 30 series resistance in both
High and Low output stages. This design reduces the line noise in
applications such as memory address drivers, clock drivers and bus
receivers/transmitters. The series termination resistors reduce
overshoot and undershoot and are ideal for driving memory arrays.
QUICK REFERENCE DATA
CONDITIONS
TYPICAL
T
amb
= 25°C
2.5V 3.3V
t
PLH
t
PHL
Propagation delay
nCP to nQ
C
L
= 50pF
4.4
3.8
3.2
3.2
ns
C
IN
Input capacitance V
I
= 0V or V
CC
3 3 pF
C
OUT
Output capacitance V
O
= 0 or V
CC
9 9 pF
I
CCZ
Total supply current Outputs disabled 40 70 µA
ORDERING INFORMATION
PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER
56-Pin Plastic SSOP Type III –40°C to +85°C 74ALVT162821 DL AV162821 DL SOT371-1
56-Pin Plastic TSSOP Type II –40°C to +85°C 74ALVT162821 DGG AV162821 DGG SOT364-1
