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309RLF

P1-P3P4-P6P7-P9P10-P10
DATASHEET
SERIAL PROGRAMMABLE TRIPLE PLL SS VERSACLOCK SYNTH ICS309
IDT®
SERIAL PROGRAMMABLE TRIPLE PLL SS VERSACLOCK SYNTH 1
ICS309 REV L 091311
Description
The ICS309 is a versatile serially-programmable, triple
PLL with spread spectrum clock source. The ICS309
can generate any frequency from 250kHz to 200 MHz,
and up to 6 different output frequencies simultaneously.
The outputs can be reprogrammed on-the-fly, and will
lock to a new frequency in 10 ms or less.
To reduce system EMI emissions, spread spectrum is
available that supports modulation frequencies of
31 kHz and 120 kHz, as well as modulation amplitudes
of +/-0.25% to +/-2.0%. Both center and down-spread
options are available.
The device includes a PDTS
pin which tri-states the
output clocks and powers down the entire chip.
The ICS309 default for non-programmed start-up are
buffered reference clock outputs on all clock output
pins.
IDT’s VersaClock
TM
programming software allows the
user to configure up to 9 outputs with target
frequencies, spread spectrum capabilities or buffered
reference clock outputs. The VersaClock
TM
software
automatically configures the PLLs for optimal overall
performance.
Features
• Packaged in 20-pin SSOP (QSOP) – Pb-free, RoHS
compliant
• Highly accurate frequency generation
•M/N Multiplier PLL: M = 1..2048, N = 1..1024
• Serially programmable: user determines the output
frequency via a 3-wire interface
• Spread Spectrum frequency modulation for reduced
system EMI
•Center or Down Spread up to 4% total
•Selectable 32 kHz and 120 kHz modulation
• Eliminates need for custom quartz oscillators
• Input crystal frequency of 5 - 27 MHz
• Input clock frequency of 3 - 50 MHz
• Output clock frequencies up to 200 MHz
• Operating voltage of 3.3 V
• Up to 9 reference clock outputs
• Power down tri-state mode
• Very low jitter
Block Diagram
Crystal
Oscillator
PLL1 with
Spread
Spectrum
GND
2
3
VDD
PDTS
PLL2
PLL3
Divide
Logic
and
Output
Enable
Control
CLK1
CLK9
CLK8
CLK7
CLK6
CLK5
CLK4
CLK3
CLK2
X2
Crystal or
clock input
External capacitors are
required with a crystal input.
X1/ICLK
SCLK
DATA
STROBE
ICS309
SERIAL PROGRAMMABLE TRIPLE PLL SS VERSACLOCK SYNTH SER PROG CLOCK SYNTHESIZER
IDT®
SERIAL PROGRAMMABLE TRIPLE PLL SS VERSACLOCK SYNTH 2
ICS309 REV L 091311
Pin Assignment
Pin Descriptions
16
1
15
2
14
DATA STROBE
3
13
X2
4
12
X1/ICLK
SCLK
5
11
CLK9
6
PDTS
7
VDD
8
GND
VDD
VDD
GND
CLK1
CLK5
CLK2
CLK6
9
10
CLK3
CLK7
CLK4
CLK8
20
19
18
17
20 pin (150 mil) SSOP (QSOP)
Pin
Number
Pin
Name
Pin
Type
Pin Description
1 DATA Input Serial data input.
2 X2 XO Crystal Output. Connect this pin to a crystal. Float for clock input.
3 X1/ICLK XI Connect this pin to a crystal or external clock input.
4 CLK9 Output Output clock 9. Default of Reference frequency output when unprogrammed.
5 VDD Power Connect to +3.3V.
6 GND Power Connect to Ground.
7 CLK1 Output Output clock 1. Default of Reference frequency output when unprogrammed.
8 CLK2 Output Output clock 2. Default of Reference frequency output when unprogrammed.
9 CLK3 Output Output clock 3. Default of Reference frequency output when unprogrammed.
10 CLK4 Output Output clock 4. Default of Reference frequency output when unprogrammed.
11 CLK8 Output Output clock 8. Default of Reference frequency output when unprogrammed.
12 CLK7 Output Output clock 7. Default of Reference frequency output when unprogrammed.
13 CLK6 Output Output clock 6. Default of Reference frequency output when unprogrammed.
14 CLK5 Output Output clock 5. Default of Reference frequency output when unprogrammed.
15 GND Power Connect to Ground.
16 VDD Power Connect to +3.3 V.
17 VDD Power Connect to +3.3 V.
18 PDTS
Input Powers down entire chip, tri-states all outputs when low. Internal pull-up.
19 SCLK Input Serial Shift register clock. See timing diagram.
20 STROBE Input Strobe to load data. See timing diagram. Use external 250 kOhm pull-up.
ICS309
SERIAL PROGRAMMABLE TRIPLE PLL SS VERSACLOCK SYNTH SER PROG CLOCK SYNTHESIZER
IDT®
SERIAL PROGRAMMABLE TRIPLE PLL SS VERSACLOCK SYNTH 3
ICS309 REV L 091311
Configuring the ICS309
Initial State: The ICS309 may be configured to have up to 9 frequency outputs, utilizing the 4 on-board
PLLs and spread spectrum circuitry. Unprogrammed, the part has the following outputs, related to the
reference input clock:
The STROBE pin must have an external 250 kOhm pull-up resistor to acheive the Initial State.
The input crystal range for the ICS309 is 5 MHz to 27 MHz.
The ICS309 can be programmed to set the output functions and frequencies. 160 data bits generated by
the VersaClock
TM
software are written in DATA pin in this order: MSB (left most bit) first.
As show in Figure 2, after these 160 bits are clocked into the ICS309, taking STROBE high will send this
data to the internal latch and the CLK output will lock within 10 ms.
Note: STROBE utilizes a transparent latch that is latched when in the high state. If STROBE is in the high
state and SCLK is pulsed, DATA is clocked directly to the internal latch and the output conditions will
change accordingly. Although this will not damage the ICS309, it is recommended that STROBE be kept
low while DATA is being clocked into the ICS309 in order to avoid unintended changes on the output clocks.
All outputs may be turned off during initialization by bringing the PDTS
pin to Ground. When PDTS is
brought high, after the Strobe pin in brought high, the programmed output frequencies will be available.
AC Parameters for Writing to the ICS309
Default Outputs
Output Frequency
Clocks 1 - 9 (Pins 4, 7-14) Reference Output
Parameter Condition Min. Max. Units
t
SETUP
Setup time 10 ns
t
HOLD
Hold time after SCLK 10 ns
t
W
Data wait time 10 ns
t
S
Strobe pulse width 40 ns
SCLK Frequency 30 MHz
DATA
t
hold
t
setup
SCLK
STROBE
t
s
t
w
Figure 2. Timing Diagram for Programming the ICS309
Bit160 Bit2 Bit1
Bit3
Bit159 Bit158
P1-P3P4-P6P7-P9P10-P10

309RLF

Mfr. #:
Buy 309RLF
Manufacturer:
IDT
Description:
Clock Synthesizer / Jitter Cleaner SERIAL PROGRAMMABLE TRIPLE PLL SS VERSAC
Lifecycle:
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