MAX3815
A squelching function can be created by sending the
CLKLOS output through an inverter to the OUTON pin.
This will squelch the CML outputs whenever the clock
signal is removed. A loss-of-signal LED indicator can
be incorporated into the circuit as well (see Figure 3).
Output Level Control (OUTLEVEL) Input
The OUTLEVEL pin is an LVTTL input that allows the
user to select between standard output amplitude
(1000mV
P-P
differential) or one-half output amplitude
(500mV
P-P
differential). Forcing this pin high results in
the standard output signal level, and forcing this pin
low results in the reduced output signal level.
Equalizer Control (EQCONTROL) Input
The EQCONTROL pin allows the user to control the
equalization in one of three ways: forcing the pin to
ground sets the equalizer in automatic equalization
mode, forcing the pin to V
CC
/ 2 sets the equalizer to
minimum equalization, and forcing a voltage between
V
CC
- 1V to V
CC
allows manual control of the equaliza-
tion level applied to the input signals. See the
Typical
Operating Characteristics
for more information.
Power-Down (
PWRDWN
) Input
The PWRDWN pin allows the part to be powered down
to reduce system power consumption. Force the pin
high for normal operation. Force the pin low to power-
down the IC. When powered down, the part consumes
approximately 10mA.
Output On (
OUTON
) Input
The OUTON pin is an LVTTL input. Force the pin low to
enable the outputs. Force the pin high to set a differential
zero on the outputs. When disabled, the outputs will go to
a differential zero, irrespective of the signal at the inputs.
Cable Selection
TMDS performance is heavily dependent on cable
quality. Deterministic jitter (DJ) can be caused by dif-
ferential-to-common-mode conversion (or vice-versa)
TMDS Digital Video Equalizer for DVI/HDMI
Cables
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