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CY2313ANZSXC-1T

P1-P3P4-P6P7-P8
CY2313ANZ
Document #: 38-07144 Rev. *B Page 4 of 8
Switching Characteristics
[4]
Over the Operating Range
Parameter Name Test Conditions Min. Typ. Max. Unit
Maximum Operating Frequency 100 MHz
Duty Cycle
[3,5]
= t
2
÷ t
1
Measured at 1.5V 45.0 50.0 55.0 %
t
3
Rising Edge Rate
[3]
Measured between 0.4V and 2.4V 0.9 1.5 4.0 V/ns
t
4
Falling Edge Rate
[3]
Measured between 2.4V and 0.4V 0.9 1.5 4.0 V/ns
t
5
Output to Output Skew
[3]
All outputs equally loaded –250 +250 ps
t
6
SDRAM Buffer LH Prop. Delay
[3]
Input edge greater than 1 V/ns 1.0 3.5 5.0 ns
t
7
SDRAM Buffer HL Prop. Delay
[3]
Input edge greater than 1 V/ns 1.0 3.5 5.0 ns
t
8
SDRAM Buffer Enable Delay
[3]
Input edge greater than 1 V/ns 1.0 5 12 ns
t
9
SDRAM Buffer Disable Delay
[3]
Input edge greater than 1 V/ns 1.0 20 30 ns
Notes:
4. All parameters specified with loaded outputs.
5. Duty cycle of input clock is 50%. Rising and falling edge rate of the input clock is greater than 1 V/ns.
Switching Waveforms
Duty Cycle Timing
t
1
t
2
1.5V 1.5V 1.5V
All Outputs Rise/Fall Time
OUTPUT
t
3
3.3V
0V
0.4V
2.4V 2.4V
0.4V
t
4
Output-Output Skew
1.5V
t
5
OUTPUT
OUTPUT
1.5V
CY2313ANZ
Document #: 38-07144 Rev. *B Page 5 of 8
Switching Waveforms (continued)
SDRAM Buffer LH and HL Propagation Delay
t
6
INPUT
OUTPUT
t
7
t
8
OE
OUTPUTS
SDRAM Buffer Enable and Disable Times
t
9
Three-State
Active
0.1 μF
V
DD
CLK out
C
LOAD
OUTPUTS
GND
Test Circuit
CY2313ANZ
Document #: 38-07144 Rev. *B Page 6 of 8
Application Information
Clock traces must be terminated with either series or parallel termination, as is normally done.
Summary
• Surface mount, low-ESR, ceramic capacitors should be used for filtering. Typically, these capacitors have a value of 0.1 μF.
In some cases, smaller value capacitors may be required.
• The value of the series terminating resistor satisfies the following equation, where Rtrace is the loaded characteristic impedance
of the trace, Rout is the output impedance of the buffer (typically 25Ω), and Rseries is the series terminating resistor.
Rseries > Rtrace – Rout
• Footprints must be laid out for optional EMI-reducing capacitors, which should be placed as close to the terminating resistor
as is physically possible. Typical values of these capacitors range from 4.7 pF to 22 pF.
• A Ferrite Bead may be used to isolate the Board V
DD
from the clock generator V
DD
island. Ensure that the Ferrite Bead offers
greater than 50Ω impedance at the clock frequency, under loaded DC conditions. Please refer to the application note “Layout
and Termination Techniques for Cypress Clock Generators” for more details.
• If a Ferrite Bead is used, a 10 μF–22 μF tantalum bypass capacitor should be placed close to the Ferrite Bead. This capacitor
prevents power supply droop during current surges.
Application Circuit
CY2313A: 28-PIN SOIC
Ordering Information
Ordering Code
Package
Name Package Type
Operating
Range
CY2313ANZSC–1 S21 28-Pin SOIC Commercial
Pb-free
CY2313ANZSXC–1 S21 28-Pin SOIC Commercial
CY2313ANZSXC–1T S21 28-Pin SOIC Tape and Reel Commercial
P1-P3P4-P6P7-P8

CY2313ANZSXC-1T

Mfr. #:
Buy CY2313ANZSXC-1T
Manufacturer:
Cypress Semiconductor
Description:
IC CLK BUFF 13OUT SDRAM 28SOIC
Lifecycle:
New from this manufacturer.
Delivery:
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