MC44608
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8
2. Overload
In the hiccup mode the 3 distinct phases are described as
follows (refer to Figure 7):
The SWITCHING PHASE: The SMPS output is low and
the regulation block reacts by increasing the ON time (dmax
= 80%). The OC is reached at the end of every switching
cycle. The LW latch (Figure 8) is reset before the VPWM
signal appears. The SMPS output voltage is low. The V
CC
voltage cannot be maintained at a normal level as the
auxiliary winding provides a voltage which is also reduced
in a ratio similar to the one on the output (i.e. Vout nominal
/ Vout short--circuit). Consequently the V
CC
voltage is
reduced at an operating rate given by the combination V
CC
capacitor value together with the I
CC
working consumption
(3.2 mA) according to the equation 2. When V
CC
crosses
10V the WORKING PHASE gets terminated. The LW latch
remains in the reset status.
The LATCHED--OFF PHASE: The V
CC
capacitor
voltage continues to drop. When it reaches 6.5 V this phase
is terminated. Its duration is governed by equation 3.
The startup PHASE is reinitiated. The high voltage startup
current source (--I
CC1
= 9.0 mA) is activated and the MODE
latch is reset. The V
CC
voltage ramps up according to the
equation 1. When it reaches 13 V, the IC enters into the
SWITCHING PHASE.
The NEXT SWITCHING PHASE: The high voltage
current source is inhibited, the MODE latch (Q=0) activates
the NORMAL mode of operation. Figure 3 shows that no
current is injected out pin 2. The over current sense level
corresponds to 1.0 V.
As long as the overload is present, this sequence repeats.
The SWITCHING PHASE duty cycle is in the range of 10%.
3. Transition from Normal to Pulsed Mode
In this sequence the secondary side is reconfigured (refer
to the typical application schematic on page 13). The high
voltage output value becomes lower than the NORMAL
mode regulated value. The TL431 shunt regulator is fully
OFF. In the SMPS standby mode all the SMPS outputs are
lowered except for the low voltage output that supply the
wake--up circuit located at the isolated side of the power
supply. In that mode the secondary regulation is performed
by the zener diode connected in parallel to the TL431.
The secondary reconfiguration status can be detected on
the SMPS primary side by measuring the voltage level
present on the auxiliary winding Laux. (Refer to the
Demagnetization Section). In the reconfigured status, the
Laux voltage is also reduced. The V
CC
self--powering is no
longer possible thus the SMPS enters in a hiccup mode
similar to the one described under the Overload condition.
In the SMPS standby mode the 3 distinct phases are:
The SWITCHING PHASE: Similar to the Overload
mode. The current sense clamping level is reduced
according to the equation of the current sense section,
page 5. The C.S. clamping level depends on the power to be
delivered to the load during the SMPS standby mode. Every
switching sequence ON/OFF is terminated by an OC as long
as the secondary Zener diode voltage has not been reached.
When the Zener voltage is reached the ON cycle is
terminated by a true PWM action. The proper SWITCHING
PHASE termination must correspond to a NOC condition.
The LW latch stores this NOC status.
The LATCHED OFF PHASE: The MODE latch is set.
The startup PHASE is similar to the Overload Mode. The
MODE latch remains in its set status (Q=1).
The SWITCHING PHASE: The standby signal is
validated and the 200 mA is sourced out of the Current Sense
pin 2.
4. Transition from Standby to Normal
The secondary reconfiguration is removed. The
regulation on the low voltage secondary rail can no longer
be achieved, thus at the end of the SWITCHING PHASE, no
PWM condition can be encountered. The LW latch is reset.
At the next WORKING PHASE a NORMAL mode status
takes place.
In order to become independent of the recovery time
constant on the secondary side of the SMPS an additional
reset input R2 is provided on the MODE latch. The condition
Idemag<24 mA corresponds to the activation of the
secondary reconfiguration status. The R2 reset insures a
direct return into the Normal Mode.
Pulsed Mode Duty Cycle Control
During the sleep mode of the SMPS the switch S3 is
closed and the control input pin 3 is connected to a 4.6 V
voltage source thru a 500 Ω resistor. The discharge rate of
the V
CC
capacitor is given by I
CC--latc h
(device consumption
during the LATCHED OFF phase) in addition to the current
drawn out of the pin 3. Connecting a resistor between the
Pin 3 and GND (R
DPULSED
) a programmable current is
drawn from the V
CC
through pin 3. The duration of the
LATCHED OFF phase is impacted by the presence of the
resistor R
DPULSED
. The equation 3 shows the relation to the
pin 3 current.
Pulsed Mode Phases
Equations 1 through 8 define and predict the effective
behavior during the PULSED MODE operation. The
equations 6, 7, and 8 contain K, Y, and D factors. These
factors are combinations of measured parameters. They
appear in the parameter section “Kfactors for pulsed mode
operation” page 4. In equations 3 through 8 the pin 3 current
is the current defined in the above section “Pulsed Mode
Duty Cycle Control”.
