MC74ACT273NG

© Semiconductor Components Industries, LLC, 2016
December, 2016 − Rev. 8
1 Publication Order Number:
MC74AC273/D
MC74AC273, MC74ACT273
Octal D Flip-Flop
The MC74AC273/74ACT273 has eight edge-triggered D−type
flip−flops with individual D inputs and Q outputs. The common
buffered Clock (CP) and Master Reset (MR
) inputs load and reset
(clear) all flip−flops simultaneously.
The register is fully edge-triggered. The state of each D input, one
setup time before the LOW−to−HIGH clock transition, is transferred
to the corresponding flip−flop’s Q output.
All outputs will be forced LOW independently of Clock or Data
inputs by a LOW voltage level on the MR
input. The device is useful
for applications where the true output only is required and the Clock
and Master Reset are common to all storage elements.
Features
Ideal Buffer for MOS Microprocessor or Memory
Eight Edge-Triggered D Flip−Flops
Buffered Common Clock
Buffered, Asynchronous Master Reset
See MC74AC377 for Clock Enable Version
See MC74AC373 for Transparent Latch Version
See MC74AC374 for 3-State Version
Outputs Source/Sink 24 mA
ACT273 Has TTL Compatible Inputs
These are Pb−Free Devices
Pinout: 20−Lead Packages Conductors
1920 18 17 16 15 14
21 34567
V
CC
13
8
12
9
11
10
Q
7
D
7
D
6
Q
6
Q
5
D
5
D
4
Q
4
CP
MR
Q
0
D
0
D
1
Q
1
Q
2
D
2
D
3
Q
3
GND
(Top View)
MODE SELECT-FUNCTION TABLE
Operating Mode
Inputs Outputs
MR CP D
n
Q
n
Reset (Clear) L X X L
Load 1 H H H
Load 0 H L L
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= LOW-to-HIGH Clock Transition
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See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
ORDERING INFORMATION
TSSOP−20
SUFFIX DT
CASE 948E
SOIC−20WB
SUFFIX DW
CASE 751D
1
1
See general marking information in the device marking
section on page 6 of this data sheet.
DEVICE MARKING INFORMATION
20
20
PIN ASSIGNMENT
PIN
D
0
−D
7
FUNCTION
Data Inputs
MR Master Reset
CP Clock Pulse Input
Q
0
−Q
7
Data Outputs
Q
0
Q
1
Q
2
Q
3
Q
4
Q
5
Q
6
Q
7
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
CP
MR
Logic Symbol
MC74AC273, MC74ACT273
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2
Figure 1. Logic Diagram
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
O
0
O
1
O
2
O
3
O
4
O
5
O
6
O
7
DQ
CP
R
D
DQ
CP
R
D
DQ
CP
R
D
DQ
CP
R
D
DQ
CP
R
D
DQ
CP
R
D
DQ
CP
R
D
DQ
CP
R
D
CP
MR
NOTE: That this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
MC74AC273, MC74ACT273
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3
MAXIMUM RATINGS
Symbol Parameter Value Unit
V
CC
DC Supply Voltage (Referenced to GND) −0.5 to +7.0 V
V
IN
DC Input Voltage (Referenced to GND) −0.5 to V
CC
+0.5 V
V
OUT
DC Output Voltage (Referenced to GND) (Note 1) −0.5 to V
CC
+0.5 V
I
IK
DC Input Diode Current ±20 mA
I
OK
DC Output Diode Current ±50 mA
I
OUT
DC Output Sink/Source Current ±50 mA
I
CC
DC Supply Current, per Output Pin ±50 mA
I
GND
DC Ground Current, per Output Pin ±100 mA
T
STG
Storage Temperature Range *65 to )150
_C
T
L
Lead temperature, 1 mm from Case for 10 Seconds 260
_C
T
J
Junction Temperature Under Bias 140
_C
q
JA
Thermal Resistance (Note 2) SOIC
TSSOP
65.8
110.7
_C/W
MSL Moisture Sensitivity SOIC
TSSOP
Level 3
Level 1
F
R
Flammability Rating Oxygen Index: 30% − 35% UL 94 V−0 @ 0.125 in
V
ESD
ESD Withstand Voltage Human Body Model (Note 3)
Machine Model (Note 4)
Charged Device Model (Note 5)
> 2000
> 200
> 1000
V
I
Latchup
Latchup Performance Above V
CC
and Below GND at 85_C (Note 6)
±100 mA
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. I
OUT
absolute maximum rating must be observed.
2. The package thermal impedance is calculated in accordance with JESD 51−7.
3. Tested to EIA/JESD22−A114−A.
4. Tested to EIA/JESD22−A115−A.
5. Tested to JESD22−C101−A.
6. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Typ Max Unit
V
CC
Supply Voltage
AC 2.0 5.0 6.0
V
ACT 4.5 5.0 5.5
V
in
, V
out
DC Input Voltage, Output Voltage (Ref. to GND) 0 V
CC
V
t
r
, t
f
Input Rise and Fall Time (Note 7)
AC Devices except Schmitt Inputs
V
CC
@ 3.0 V 150
V
CC
@ 4.5 V 40 ns/V
V
CC
@ 5.5 V 25
t
r
, t
f
Input Rise and Fall Time (Note 8)
ACT Devices except Schmitt Inputs
V
CC
@ 4.5 V 10
ns/V
V
CC
@ 5.5 V 8.0
T
A
Operating Ambient Temperature Range −40 25 85 °C
I
OH
Output Current − High −24 mA
I
OL
Output Current − Low 24 mA
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
7. V
IN
from 30% to 70% V
CC
; see individual Data Sheets for devices that differ from the typical input rise and fall times.
8. V
IN
from 0.8 V to 2.0 V; see individual Data Sheets for devices that differ from the typical input rise and fall times.

MC74ACT273NG

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Flip Flops 5V CMOS Octal D-Type
Lifecycle:
New from this manufacturer.
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