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ACPL-P302-500E

P1-P3P4-P6P7-P9P10-P12P13-P14
10
+
-
500 W
I
F
= 7 to 16 mA
+
-
V
CC
= 15
to 30 V
75 W
1.5 nF
V
O
61
52
43
0.1 mF
10 KHz
50% DUTY
CYCLE
+
-
+
-
1
2
3
+
-
+
-
1
2
3
1
2
3
A
+
-
I
F
+
-
V
CC
= 30V
V
O
61
52
43
0.1 mF
V
CM
= 1000V
5 V
+
-
B
+
-
+
-
+
-
+
-
+
-
+
-
Figure 13. Transfer characteristics. Figure 14. Input Current vs. Forward Voltage.
Figure 15. Propagation Delay Test Circuit and Waveforms.
Figure 16. CMR Test Circuit and Waveforms.
V
O
– OUTPUT VOLTAGE – V
0
-5
I
F
– FORWARD LED CURRENT – mA
6
25
15
1
35
234
5
5
0
10
20
30
I
F
– FORWARD CURRENT – mA
1.2
0
V
F
– FORWARD VOLTAGE – V
1.8
25
1.4 1.6
5
10
15
20
I
F
V
OUT
t
PHL
t
PLH
t
f
t
r
10%
50%
90%
V
CM
Δt
0 V
V
O
SWITCH AT B: I
F
= 0 mA
V
O
SWITCH AT A: I
F
= 10 mA
V
OL
V
OH
Δt
V
CM
δV
δt
=
11
Applications Information
Eliminating Negative IGBT Gate Drive
To keep the IGBT rmly o, the ACPL-P302/W302 has a
very low maximum V
OL
specication of 1.0 V. Minimizing
R
g
and the lead inductance from the ACPL-P302/W302
to the IGBT gate and emitter (possibly by mounting the
ACPL-P302/W302 on a small PC board directly above the
IGBT) can eliminate the need for negative IGBT gate drive
in many applications as shown in Figure 17. Care should
be taken with such a PC board design to avoid routing the
IGBT collector or emitter traces close to the ACPL-P302/
W302 input as this can result in unwanted coupling of
transient signals into the input of ACPL-P302/W302 and
degrade performance. (If the IGBT drain must be routed
near the ACPL-P302/W302 input, then the LED should be
reverse biased when in the o state, to prevent the tran-
sient signals coupled from the IGBT drain from turning on
the ACPL-P302/W302.
Selecting the Gate Resistor (Rg)
Step 1: Calculate R
g
minimum from the I
OL
peak speci-
cation. The IGBT and R
g
in Figure 17 can be analyzed as
a simple RC circuit with a voltage supplied by the ACPL-
P302/W302.
Figure 18. Energy Dissipated in the ACPL-P302/W302 and for Each IGBT
Switching Cycle.
Figure 17. Recommended LED Drive and Application Circuit for ACPL-P302/W302
R
g
270Ω
V
CC
= 24V
+
-
61
52
43
0.1 μF
+5 V
CONTROL
INPUT
74XXX
OPEN
COLLECTOR
+ HVD
-HVD
3-PHA S E
AC
Q1
Q2
ACPL-P302/W302
+
-
where K
ICC
· Q
g
· f is the increase in I
CC
due to switching
and K
ICC
is a constant of 0.001 mA/(nC*kHz). For the circuit
in Figure 17 with I
F
(worst case) = 10 mA, R
g
= 57.5 :, Max
Duty Cycle = 80%, Q
g
= 100 nC, f = 20 kHz and T
AMAX
=
85°C:
57.5 Ω
0.4
24 − 1
I
VV
R
OLPEAK
OLCC
g
=
=
−
³
(R )
u
f
)(R)
fQ;EVfQK
Q;EVIPP
DutyCycleVP
PP
ggSWCCgICCCCBIAS
ggSWCCCCO(SWITCHING)O(BIAS)O
FFE
OET
u+uuu+= (I
+u=+= P
uu= I
+= P
The V
OL
value of 1 V in the previous equation is the V
OL
at
the peak current of 0.4A. (See Figure 4).
Step 2: Check the ACPL-P302/W302 power dissipation and
increase R
g
if necessary. The ACPL-P302/W302 total power
dissipation (P
T
) is equal to the sum of the emitter power
(P
E
) and the output power (P
O
).
@85 °C)0.3
μ
J
u
20 kHz = 126 mW £ 250 mW ( P
P
P
O(MAX)
O
E
= (3 mA + (0.001 mA/nC
u
kHz)
u
20 kHz
u
100 nC)
u
24V +
= 10 mA
u
1.8V
u
0.8 = 14 mW
The value of 3 mA for I
CC
in the previous equation is the
max. I
CC
over entire operating temperature range.
Since P
O
for this case is less than P
O(MAX)
, R
g
= 57.5 : is
alright for the power dissipation.
Esw – ENERGY PER SWITCHING CYCLE – μJ
0
0
Rg – GATE RESISTANCE – Ω
100
1.5
20
4.0
40
1.0
60 80
3.5
Qg = 50 nC
Qg = 100 nC
Qg = 200 nC
Qg = 400 nC
3.0
2.0
0.5
2.5
12
CMR with the LED On (CMR
H
)
A high CMR LED drive circuit must keep the LED on during
common mode transients. This is achieved by overdriv-
ing the LED current beyond the input threshold so that
it is not pulled below the threshold during a transient. A
minimum LED current of 7 mA provides adequate margin
over the maximum I
FLH
of 5 mA to achieve 10 kV/μs CMR.
LED Drive Circuit Considerations for Ultra High CMR Per-
formance
Without a detector shield, the dominant cause of opto-
coupler CMR failure is capacitive coupling from the input
side of the optocoupler, through the package, to the
detector IC as shown in Figure 19. The ACPL-P302/W302
improves CMR performance by using a detector IC with
an optically transparent Faraday shield, which diverts the
capacitively coupled current away from the sensitive IC
circuitry. However, this shield does not eliminate the ca-
pacitive coupling between the LED and optocoupler pins
5-8 as shown in Figure 20. This capacitive coupling causes
perturbations in the LED current during common mode
transients and becomes the major source of CMR failures
for a shielded optocoupler. The main design objective of
a high CMR LED drive circuit becomes keeping the LED in
the proper state (on or o) during common mode tran-
sients. For example, the recommended application circuit
(Figure 17), can achieve 10 kV/μs CMR while minimizing
component complexity.
Techniques to keep the LED in the proper state are dis-
cussed in the next two sections.
Figure 21. Equivalent Circuit for Figure 15 During Common Mode Transient.
The open collector drive circuit, shown in Figure 22, can
not keep the LED o during a +dV
CM
/dt transient, since
all the current owing through C
LEDN
must be supplied
by the LED, and it is not recommended for applications
requiring ultra high CMR
L
performance. The alternative
drive circuit which like the recommended application
circuit (Figure 17), does achieve ultra high CMR perfor-
mance by shunting the LED in the o state.
Figure 19. Optocoupler Input to Output Capacitance Model for Unshielded
Optocouplers.
Figure 20. Optocoupler Input to Output Capacitance Model for Shielded
Optocouplers.
Figure 22. Not Recommended Open Collector Drive Circuit.
CMR with the LED O (CMR
L
)
A high CMR LED drive circuit must keep the LED o (V
F
d V
F(OFF)
) during common mode transients. For example,
during a -dV
CM
/dt transient in Figure 21, the current
owing through C
LEDP
also ows through the R
SAT
and
V
SAT
of the logic gate. As long as the low state voltage de-
veloped across the logic gate is less than V
F(OFF)
the LED
will remain o and no common mode failure will occur.
Figure 23. Recommended LED Drive Circuit for Ultra-High CMR Dead Time
and Propagation Delay Specications.
C
LEDP
C
LEDN
61
52
43
C
LEDP
C
LEDN
61
52
43
C
LEDP
C
LEDN
61
52
43
SHIELD
C
LED01
C
LED02
C
LEDP
C
LEDN
61
52
43
SHIELD
C
LED01
C
LED02
C
LED P
C
LED N
61
52
43
SHIELD
I
LED P
R
g
V
CC
= 18V
+
-
0.1 mF
+
-
THE ARROWS INDICATE THE DIREC TI ON
OF CURRENT FLOW DURING - dV
CM
/ dt
+5 V
V
SAT
+
-
V
CM
I
+
-
+
-
V
SAT
+
-
V
SAT
+
-
·
·
C
LEDP
C
LEDN
61
52
43
SHIELD
I
LEDN
+5 V
Q1
C
LEDP
C
LEDN
61
52
43
SHIELD
I
LEDN
+5 V
Q1Q1
C
LEDP
C
LEDN
61
52
43
SHIELD
+5 V
C
LEDP
C
LEDN
61
52
43
+5 V
P1-P3P4-P6P7-P9P10-P12P13-P14

ACPL-P302-500E

Mfr. #:
Buy ACPL-P302-500E
Manufacturer:
Broadcom / Avago
Description:
Logic Output Optocouplers 0.4A IGBT Gate Drive
Lifecycle:
New from this manufacturer.
Delivery:
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