DS1554P-70+ Datasheet DS1554-70+, DS1554WP-120IND+, DS1554P-70IND+ | P7-P9

DS1554 256k, Nonvolatile, Y2K-Compliant Timekeeping RAM

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Table 2. Register Map

DATA

ADDRESS

FUNCTION/RANGE

7FFFh 10 Year Year Year 00-99

7FFEh X X X

Month

Month Month 01-12

7FFDh X X 10 Date Date Date 01-31

7FFCh X FT X X X Day Day 01-07

7FFBh X X 10 Hour Hour Hour 00-23

7FFAh X 10 Minutes Minutes Minutes 00-59

7FF9h

OSC

10 Seconds Seconds Seconds 00-59

7FF8h W R 10 Century Century Control 00-39

7FF7h WDS BMB4 BMB3 BMB2 BMB1 BMB0 RB1 RB0 Watchdog —

7FF6h AE Y ABE Y Y Y Y Y Interrupts —

7FF5h AM4 Y 10 Date Date Alarm Date 01-31

7FF4h AM3 Y 10 Hours Hours Alarm Hours 00-23

7FF3h AM2 10 Minutes Minutes Alarm Minutes 00-59

7FF2h AM1 10 Seconds Seconds Alarm Seconds 00-59

7FF1h Y Y Y Y Y Y Y Y Unused —

7FF0h WF AF 0 BLF 0 0 0 0 Flags —

X = Unused, Read/Writeable under Write and Read Bit Control AE = Alarm Flag Enable

Y = Unused, Read/Writeable without Write and Read Bit Control ABE = Alarm in Battery-Backup Mode Enable

FT = Frequency Test Bit AM1-AM4 = Alarm Mask Bits

OSC = Oscillator Start/Stop Bit

WF = Watchdog Flag

W = Write Bit AF = Alarm Flag

R = Read Bit 0 = 0 (Read Only)

WDS = Watchdog Steering Bit BLF = Battery Low Flag

BMB0 to BMB4 = Watchdog Multiplier Bits RB0 to RB1 = Watchdog Resolution Bits

CLOCK OSCILLATOR CONTROL

The Clock oscillator may be stopped at any time. To increase the shelf life of the backup lithium battery

source, the oscillator can be turned off to minimize current drain from the battery. The OSC bit is the

MSB of the Seconds Register (B7 of 7FF9h). Setting it to a 1 stops the oscillator, setting to a 0 starts the

oscillator. The DS1554 is shipped from Maxim with the clock oscillator turned off, OSC bit set to a 1.

READING THE CLOCK

When reading the RTC data, it is recommended to halt updates to the external set of double-buffered RTC

Registers. This puts the external registers into a static state allowing data to be read without register

values changing during the read process. Normal updates to the internal registers continue while in this

state. External updates are halted when a 1 is written into the read bit, B6 of the Control Register (7FF8h).

As long as a 1 remains in the Control Register read bit, updating is halted. After a halt is issued, the

registers reflect the RTC count (day, date, and time) that was current at the moment the halt command

was issued. Normal updates to the external set of registers will resume within 1 second after the read bit is

set to a 0 for a minimum of 500 s. The read bit must be a zero for a minimum of 500 s to ensure the

external registers will be updated.

DS1554 256k, Nonvolatile, Y2K-Compliant Timekeeping RAM

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SETTING THE CLOCK

The 8th bit, B7 of the Control Register is the write bit. Setting the write bit to a 1, like the read bit, halts

updates to the DS1554 (7FF8h-7FFFh) registers. After setting the write bit to a 1, RTC Registers can be

loaded with the desired RTC count (day, date, and time) in 24-hour BCD format. Setting the write bit to a

0 then transfers the values written to the internal RTC Registers and allows normal operation to resume.

CLOCK ACCURACY (DIP MODULE)

The DS1553 is guaranteed to keep time accuracy to within 1 minute per month at 25C. The RTC is

calibrated at the factory by Maxim using nonvolatile tuning elements and does not require additional

calibration. For this reason, methods of field clock calibration are not available and not necessary. The

electrical environment also affects clock accuracy. Caution should be taken to place the RTC in the

lowest-level EMI section of the PC board layout. For additional information, refer to Application Note

58.

CLOCK ACCURACY (PowerCap MODULE)

The DS1554 and DS9034PCX are each individually tested for accuracy. Once mounted together, the

module is will typically keep time accuracy to within 1.53 minutes per month (35 ppm) at 25°C. The

electrical environment affects clock accuracy. Caution should be taken to place the RTC in the lowest-

level EMI section of the PC board layout. For additional information, refer to Application Note 58.

FREQUENCY TEST MODE

The DS1554 frequency test mode uses the open drain IRQ/FT output. With the oscillator running, the

IRQ/FT output will toggle at 512 Hz when the FT bit is a 1, the Alarm Flag Enable bit (AE) is a 0, and

the Watchdog Steering bit (WDS) is a 1 or the Watchdog Register is reset (Register 7FF7h = 00h). The

IRQ/FT output and the frequency test mode can be used as a measure of the actual frequency of the

32.768 kHz RTC oscillator. The IRQ/FT pin is an open-drain output that requires a pullup resistor for

proper operation. The FT bit is cleared to a 0 on power-up.

USING THE CLOCK ALARM

The alarm settings and control for the DS1554 reside within Registers 7FF2h-7FF5h. Register 7FF6h

contains two alarm enable bits: Alarm Enable (AE) and Alarm in Backup Enable (ABE). The AE and

ABE bits must be set as described below for the IRQ /FT output to be activated for a matched alarm

condition.

The alarm can be programmed to activate on a specific day of the month or repeat every day, hour,

minute, or second. It can also be programmed to go off while the DS1554 is in the battery-backed state of

operation to serve as a system wakeup. Alarm mask bits AM1 to AM4 control the alarm mode. Table 3

shows the possible settings. Configurations not listed in the table default to the once per second mode to

notify the user of an incorrect alarm setting.

DS1554 256k, Nonvolatile, Y2K-Compliant Timekeeping RAM

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Table 3. Alarm Mask Bits

AM4 AM3 AM2 AM1 ALARM RATE

1 1 1 1 Once per second

1 1 1 0 When seconds match

1 1 0 0 When minutes and seconds match

1 0 0 0 When hours, minutes, and seconds match

0 0 0 0 When date, hours, minutes, and seconds match

When the RTC Register values match Alarm Register settings, the Alarm Flag bit (AF) is set to a 1. If

Alarm Flag Enable (AE) is also set to a 1, the alarm condition activates the IRQ/FT pin. The IRQ/FT

signal is cleared by a read or write to the Flags Register (Address 7FF0h) as shown in Figure 2 and 3.

When CE is active, the IRQ/FT signal may be cleared by having the address stable for as short as 15 ns

and either OE or WE active, but is not guaranteed to be cleared unless t

is fulfilled. The alarm flag is

also cleared by a read or write to the Flags Register but the flag will not change states until the end of the

read/write cycle and the IRQ/FT signal has been cleared.

Figure 2. Clearing IRQ Waveforms

Figure 3. Clearing IRQ Waveforms

The IRQ/FT pin can also be activated in the battery-backed mode. The IRQ/FT will go low if an alarm

occurs and both ABE and AE are set. The ABE and AE bits are cleared during the power-up transition,

however an alarm generated during power-up will set AF. Therefore, the AF bit can be read after system

power-up to determine if an alarm was generated during the power-up sequence. Figure 4 illustrates alarm

timing during the battery-backup mode and power-up states.

CE,

CE=0

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18

DS1554P-70+

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Real Time Clock 256kB NV RAM Timekeeper

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