19
FN2958.6
August 19, 2015
82C50A
BAUD GENERATOR
(29) N Baud Divisor 1 2
16
-1
(30) TBLD Baud Output Negative Edge Delay - 250 ns
(31) TBHD Baud Output Positive Edge Delay - 250 ns
(32) TLW Baud Output Down Time 40 - ns T
XL
= 50ns
(33) THW Baud Output Up Time 40 - ns T
XH
= 50ns
RECEIVER
(34) TSCD Delay from RCLK to Sample Time - 250 ns
(35) TSlNT Delay from Stop to Set Interrupt 1 1 BAUDOUT
Cycles
(36) TRlNT Delay from DISTR DISTR
(RD RBR) to
Reset Interrupt
- 250 ns
TRANSMITTER
(37) THR Delay from DOSTR DOSTR
to Reset Interrupt - 250 ns
(38) TlRS Delay from Initial INTR Reset to Transmit Start 8 24 BAUDOUT
Cycles
(39) TS1 Delay from Initial Write to Interrupt 16 32 BAUDOUT
Cycles
(40) TSTl Delay from Stop to Interrupt (THRE) 8 24 BAUDOUT
Cycles
(41) TIR Delay from DISTR DISTR
(RD lIR) to Reset Interrupt
(THRE)
- 250 ns
MODEM CONTROL
(42) TMDO Delay from DOSTR DOSTR
to Output - 500 ns
(43) TSIM Delay to Set Interrupt from Modem Input - 500 ns
(44) TRIM Delay to Reset Interrupt from DISTR DlSTR
(RD MSR)
- 500 ns
AC Electrical Specifications V
CC
= 5.0V ±10%, T
A
= 0
o
C to +70
o
C (CX82C50A-5) T
A
= -40
o
C to +85
o
C (lX82C50A-5)
Timing (Continued)
SYMBOL PARAMETER
82C50A-5
UNITS TEST CONDITIONSMIN MAX
20
FN2958.6
August 19, 2015
82C50A
AC Test Circuit AC Testing Input, Output Waveform
TEST CONDITION DEFINITION TABLE
IOH IOL V1 R1 C1
-2.5mA +2.5mA 1.7V 520 100pF
OUTPUT FROM
DEVICE UNDER TEST
TEST
C1 (NOTE)
POINT
NOTE: Includes stay and jig capacitance.
V1
R1
INPUT
V
IH
+ 0.4V
V
IL
- 0.4V
OUTPUT
V
OH
V
OL
1.5V 1.5V
AC Testing: All input signals must switch between V
IL
-0.4V and
V
IH
+0.4V. Input rise and fall times are driven at 1ns/V.
Timing Waveforms
FIGURE 3. EXTERNAL CLOCK INPUT
FIGURE 4. AC TEST POINTS
FIGURE 5. BAUDOUT
TIMING
2.0V
0.8V
tXH
(27)
XTAL1
tXL
(28)
2.0V 2.0V
0.8V0.8V
N
(29)
XTAL1
(31) tBHD
(30) tBLD
tHW (33)
tLW (32)
tLW (32)
tLW
(32)
tHW
(33)
(30)
tBLD
(30)
tBLD
(31)
tBHD
(31)
tBHD
(30)
tBLD
tLW = 2XTAL1 CYCLES
(32)
tHW = (N - 2) XTAL1 CYCLES
(33)
(31) tBHD
tHW
(33)
BAUD OUT
(1)
BAUD OUT
(2)
BAUD OUT
(3)
BAUD OUT
(N, N > 3)
NOTE: tBLD (1) is the only spec measure from XTL1 falling edge. All other tBLD’s and tBHD’s are measured from XTAL1 rising edge.
21
FN2958.6
August 19, 2015
82C50A
FIGURE 6. WRITE CYCLE
FIGURE 7. READ CYCLE
Timing Waveforms (Continued)
(1)
tAW
(2) tAS
(3) tAH
(4) tCS
(5) tCH
VALID
VALID
(17)
tCSC
(25)
tCSW
(24)
tAW
(12)
tDOW
(13)
tWC
(14)
WC
OR
ACTIVE
ACTIVE
VALID DATA
(15) tDS (16) tDH
ACTIVE
(23)
tWCS
(22) tWA
DOSTR/DOSTR
DISTR
/DISTR
DATA
D0-D7
CSOUT
CS
2, CS1, CS0
A2, A1, A0
ADS
Applicable only when ADS is tied low.

CS82C50A-5Z

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
UART Interface IC W/ANNEAL 44 PLCC 0+7 0C 5 0V 10 0MHZ
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union