CBTL05023 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 5 — 15 July 2013 5 of 19
NXP Semiconductors
CBTL05023
Multiplexer/demultiplexer switch for Thunderbolt applications
[1] HVQFN24 package die supply ground is connected to both GND pins and exposed center pad. GND pins
and the exposed center pad must be connected to supply ground for proper device operation. For
enhanced thermal, electrical, and board level performance, the exposed pad needs to be soldered to the
board using a corresponding thermal pad on the board and for proper heat conduction through the board,
thermal vias need to be incorporated in the printed-circuit board in the thermal pad region.
Control signals
HPDOUT 12 CMOS output 3.3 V CMOS output buffer for HPD.
HPD 17 CMOS input CMOS input with 5 V tolerance.
CA_DET 18 CMOS input When CA_SET is HIGH, the DDC_CLK and
DDC_DAT replace AUX differential pair.
CA_DETOUT 16 CMOS output 3.3 V CMOS output buffer for CA_DET.
BIASIN 1 CMOS input CMOS input buffer.
BIASOUT 24 CMOS output This output enables the 1 k pull-down resistors
for both AUXIO+ and AUXIO. It enables the DC
bias of the 10 Gbit/s data path. It provides power
through six sets of 3.2 k bias circuits for
10 Gbit/s paths.
AUXIO_EN 2 CMOS input If AUXIO_EN is LOW, then AUXIO+ and AUXIO
are in high-impedance state for Sleep mode.
DP_PD 6 CMOS input If DP_PD is LOW, then DPMLO+ and DPMLO
are connected to DP+ and DP. If DP_PD is
HIGH, then DPMLO+ and DPMLO are
connected to LSTX and LSRX. This multiplexer
must work during initial power-up that might have
V
DD
=2.3V.
3.3 V supply option
V
DD
3, 15 power 3.3 V supply. Both pin 3 and pin 15 must be
connected to system power supply.
Ground connections
GND 9, 21
[1]
ground 0 V (ground).
GND center
pad
ground The center pad must be connected to GND plane
for both electrical grounding and thermal relief.
Table 3. Pin description
…continued
Symbol Pin Type Description
