OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

MC74VHC74DTR2

P1-P3P4-P6P7-P8
© Semiconductor Components Industries, LLC, 2011
May, 2011 − Rev. 8
1 Publication Order Number:
MC74VHC74/D
MC74VHC74
Dual D-Type Flip-Flop
with Set and Reset
The MC74VHC74 is an advanced high speed CMOS D−type
flip−flop fabricated with silicon gate CMOS technology. It achieves
high speed operation similar to equivalent Bipolar Schottky TTL
while maintaining CMOS low power dissipation.
The signal level applied to the D input is transferred to Q output
during the positive going transition of the Clock pulse.
Reset (RD
) and Set (SD) are independent of the Clock (CP) and are
accomplished by setting the appropriate input Low.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output. The
inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V
systems to 3.0 V systems.
Features
• High Speed: f
max
= 170MHz (Typ) at V
CC
= 5V
• Low Power Dissipation: I
CC
= 2mA (Max) at T
A
= 25°C
• High Noise Immunity: V
NIH
= V
NIL
= 28% V
CC
• Power Down Protection Provided on Inputs
• Balanced Propagation Delays
• Designed for 2.0 V to 5.5 V Operating Range
• Low Noise: V
OLP
= 0.8 V (Max)
• Pin and Function Compatible with Other Standard Logic Families
• Latchup Performance Exceeds 300 mA
• ESD Performance:
Human Body Model > 2000 V;
Machine Model > 200 V
• Chip Complexity: 128 FETs or 32 Equivalent Gates
• These Devices are Pb−Free and are RoHS Compliant
Figure 1. LOGIC DIAGRAM
RD1
D1
CP1
SD1
RD2
D2
CP2
SD2
1
2
3
4
13
12
11
10
5
6
9
8
Q1
Q1
Q2
Q2
MARKING
DIAGRAMS
TSSOP−14
DT SUFFIX
CASE 948G
1
SOEIAJ−14
M SUFFIX
CASE 965
SOIC−14
D SUFFIX
CASE 751A
1
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
ORDERING INFORMATION
http://onsemi.com
A = Assembly Location
WL, L = Wafer Lot
Y, YY = Year
WW, W = Work Week
G or G = Pb−Free Package
1
14
VHC74
ALYWG
VHC74G
AWLYWW
1
14
VHC
74
ALYWG
G
1
14
(Note: Microdot may be in either location)
FUNCTION TABLE
Inputs Outputs
SD
RD CP D Q Q
LH XX HL
HL XX LH
L L X X H* H*
HH H HL
HH L LH
H H L X No Change
H H H X No Change
H H X No Change
*Both outputs will remain high as long as Set and Re-
set are low, but the output states are unpredictable
if Set and Reset go high simultaneously.
1
14
MC74VHC74
http://onsemi.com
2
SD1
CP1
D1
RD1
11
12
13
14
8
9
105
4
3
2
1
7
6
SD2
CP2
D2
RD2
V
CC
Q2
Q2
GND
Q1
Q1
Figure 2. PIN ASSIGNMENT
MAXIMUM RATINGS
Symbol Parameter Value Unit
V
CC
DC Supply Voltage – 0.5 to + 7.0 V
V
in
DC Input Voltage – 0.5 to + 7.0 V
V
out
DC Output Voltage – 0.5 to V
CC
+ 0.5 V
I
IK
Input Diode Current −20 mA
I
OK
Output Diode Current ±20 mA
I
out
DC Output Current, per Pin ±25 mA
I
CC
DC Supply Current, V
CC
and GND Pins ±50 mA
P
D
Power Dissipation in Still Air, SOIC Packages†
TSSOP Package†
500
450
mW
T
stg
Storage Temperature –65 to +150
_C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress
ratings only. Functional operation above the Recommended Operating Conditions is not implied.
Extended exposure to stresses above the Recommended Operating Conditions may affect device
reliability.
†Derating SOIC Packages: – 7 mW/_C from 65_ to 125_C
TSSOP Package: − 6.1 mW/_C from 65_ to 125_C
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
V
CC
DC Supply Voltage 2.0 5.5 V
V
in
DC Input Voltage 0 5.5 V
V
out
DC Output Voltage 0 V
CC
V
T
A
Operating Temperature, All Package Types −55 + 125
_C
t
r
, t
f
Input Rise and Fall Time V
CC
= 3.3V ±0.3V
V
CC
=5.0V ±0.5V
0
0
100
20
ns/V
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
cuit. For proper operation, V
in
and
V
out
should be constrained to the
range GND v (V
in
or V
out
) v V
CC
.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V
CC
).
Unused outputs must be left open.
MC74VHC74
http://onsemi.com
3
DC ELECTRICAL CHARACTERISTICS
Symbol Parameter Test Conditions
V
CC
V
T
A
= 25°C T
A
= −55°C to +125°C
Unit
Min Typ Max Min Max
V
IH
Minimum High−Level
Input Voltage
2.0
3.0 to 5.5
1.50
V
CC
x 0.7
1.50
V
CC
x 0.7
V
V
IL
Maximum Low−Level
Input Voltage
2.0
3.0 to 5.5
0.50
V
CC
x 0.3
0.50
V
CC
x 0.3
V
V
OH
Minimum High−Level
Output Voltage
V
in
= V
IH
or V
IL
I
OH
= − 50mA
2.0
3.0
4.5
1.9
2.9
4.4
2.0
3.0
4.5
1.9
2.9
4.4
V
V
in
= V
IH
or V
IL
I
OH
= − 4mA
I
OH
= − 8mA
3.0
4.5
2.58
3.94
2.48
3.80
V
OL
Maximum Low−Level
Output Voltage
V
in
= V
IH
or V
IL
I
OL
= 50mA
2.0
3.0
4.5
0.0
0.0
0.0
0.1
0.1
0.1
0.1
0.1
0.1
V
V
in
= V
IH
or V
IL
I
OL
= 4mA
I
OL
= 8mA
3.0
4.5
0.36
0.36
0.44
0.44
I
in
Maximum Input
Leakage Current
V
in
= 5.5V or GND 0 to 5.5 ± 0.1 ± 1.0
mA
I
CC
Maximum Quiescent
Supply Current
V
in
= V
CC
or GND 5.5 2.0 20.0
mA
AC ELECTRICAL CHARACTERISTICS (Input t
r
= t
f
= 3.0ns)
Symbol Parameter Test Conditions
T
A
= 25°C T
A
= −55°C to +125°C
Unit
Min Typ Max Min Max
t
PLH
,
t
PHL
Maximum Propagation Delay,
CP to Q or Q
V
CC
= 3.3 ± 0.3V C
L
= 15pF
C
L
= 50pF
6.7
9.2
11.9
15.4
1.0
1.0
14.0
17.5
ns
V
CC
= 5.0 ± 0.5V C
L
= 15pF
C
L
= 50pF
4.6
6.1
7.3
9.3
1.0
1.0
8.5
10.5
t
PLH
,
t
PHL
Maximum Propagation Delay,
SD
or RD to Q or Q
V
CC
= 3.3 ± 0.3V C
L
= 15pF
C
L
= 50pF
7.6
10.1
12.3
15.8
1.0
1.0
14.5
18.0
ns
V
CC
= 5.0 ± 0.5V C
L
= 15pF
C
L
= 50pF
4.8
6.3
7.7
9.7
1.0
1.0
9.0
11.0
f
max
Maximum Clock Frequency
(50% Duty Cycle)
V
CC
= 3.3 ± 0.3V C
L
= 15pF
C
L
= 50pF
80
50
125
75
70
45
MHz
V
CC
= 5.0 ± 0.5V C
L
= 15pF
C
L
= 50pF
130
90
170
115
110
75
C
in
Maximum Input Capacitance 4 10 10 pF
C
PD
Power Dissipation Capacitance (Note 1)
Typical @ 25°C, V
CC
= 5.0V
pF
25
1. C
PD
is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: I
CC(OPR
)
= C
PD
V
CC
f
in
+ I
CC
/ 2 (per flip−flop). C
PD
is used to determine the
no−load dynamic power consumption; P
D
= C
PD
V
CC
2
f
in
+ I
CC
V
CC
.
P1-P3P4-P6P7-P8

MC74VHC74DTR2

Mfr. #:
Buy MC74VHC74DTR2
Manufacturer:
ON Semiconductor
Description:
Flip Flops 2-5.5V CMOS Dual
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet