IDT5P49EE805
VERSACLOCK
®
LOW POWER CLOCK GENERATOR EEPROM CLOCK GENERATOR
IDT®
VERSACLOCK
®
LOW POWER CLOCK GENERATOR 16
IDT5P49EE805 REV H 101711
AC Timing Electrical Characteristics
(Spread Spectrum Generation = OFF)
Symbol Parameter Test Conditions Min. Typ. Max. Units
1 / t1 Output Frequency Single Ended Clock output limit (LVTTL) 3.3V 0.001 100 MHz
Single Ended Clock output limit (LVTTL) 2.5V 100 MHz
Single Ended Clock output limit (LVTTL) 1.8V 100 MHz
f
VCO
VCO Frequency VCO operating Frequency Range 100 500 MHz
f
PFD
PFD Frequency PFD operating Frequency Range 0.5
1
100 MHz
f
BW
Loop Bandwidth Based on loop filter resistor and capacitor
values
0.01 10 MHz
t2 Input Duty Cycle Duty Cycle for Input 40 60 %
t3 Output Duty Cycle Measured at VDD/2 45 55 %
Output Level - Vpp OUT6A and OUT6B 0.75 1 Vpp
t4 Slew Rate, SLEWx(bits) = 00 Single-Ended 3.3V LVCMOS Output clock rise
and fall time, 20% to 80% of VDD
(Output Load = 7 pF)
5.1 V/ns
Slew Rate, SLEWx(bits) = 01 Single-Ended 3.3V LVCMOS Output clock rise
and fall time, 20% to 80% of VDD
(Output Load = 7 pF)
4.4
Slew Rate, SLEWx(bits) = 10 Single-Ended 3.3V LVCMOS Output clock rise
and fall time, 20% to 80% of VDD
(Output Load = 7 pF)
2.8
Slew Rate, SLEWx(bits) = 11 Single-Ended 3.3V LVCMOS Output clock rise
and fall time, 20% to 80% of VDD
Output Load = 7 pF)
1.8
t5 Clock Jitter Peak-to-peak period jitter, CLK outputs
measured at VDD/2; f
PFD
>= 10 MHz
Single output frequency only.
100 ps
Peak-to-peak period jitter, CLK outputs
measured at VDD/2; f
PFD
>= 10 MHz
Multiple output frequencies switching.
200 ps
t6 Output Skew Skew between output to output on the same
bank
75 ps
Skew between any output (Same freq and IO
type, FOUT >10MHz)
200 ps
t7 Lock Time
PLL Lock Time from Power-up (using MHz
reference clock)
1
1.Time from supply voltage crosses VDD=1.62V to PLLs are locked.
520ms
PLL Lock Time from Power-up using
32.768kHz reference clock)
13 s
PLL Lock time from shutdown mode 5 10 ms
