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PIN NO. SYMBOL TYPE DESCRIPTION
1-10 DIN[9..0] I Parallel digital video data inputs
11 CLK I Parallel clock input.
12 R/T I Receive or Transmit mode select. High - CRC extraction, recalculation, comparison, error
indication, re-insertion. Low - CRC calculation, insertion, clears error flags
13 FIELD/STD I Field or Standard indication select. High - Field signals on F0, F1, F2. Low - Standard
indication on F0, F1,F2. (Refer to Table 1)
14,15 S0, S1 I Error flag select inputs. Select type of error flag to output on FL0, FL1. (Refer to Table 2)
16 RSTN I Master Reset. Active low input, which provides option to initialise internal circuitry. The
GS9001 contains power on reset circuitry that automatically initialises all internal
states including the I
2
C Interface.
19,20 A0,A1 I Device address select pins for I
2
C interface bus. (Refer to Table 3)
21 SCL I Serial Clock for I
2
C Interface bus. SCL and SDA must be connected to GND if there is no
I
2
C interface connected to the device.
22 SDA I/O Serial Data for I
2
C
Interface bus.
23 INTERRUPT O Programmable interrupt for error flag indication. Active low, open drain output. Interrupt
can be made sensitive to specific or all error flags (described in I
2
C WRITE format
section). Default is sensitive to all error flags. This output stays active until a word is read
from the device.
24-33 DOUT[0..9] O Parallel digital video data outputs
34 NO TRS O Indicates presence of invalid input data, containing no timing reference signal (TRS).
Active high output which signals absence of seven consecutive valid TRSs in the
incoming data. Returns to low state after seven consecutive valid TRSs occur. A valid
input CLK must be present for this to operate.
35 ANC DATA O Ancillary data presence indication. Active high output, indicates data presence from
ANC data header word to checksum word. Can be programmed through the I
2
C
interface to also indicate presence of TRS-ID (3FF,000,000) blocks. In this mode, output
stays high for 5 words during composite video TRS-ID and 4 words during component
EAV, SAV. In stand alone operation mode without I
2
C Interface, this feature can be
forced on ANC DATA pin by selecting address 0,1 on A1,A0 pins. (NOTE: SCL and SDA
must be connected to GND when I
2
C Interface is not used)
36 HSYNC O Horizontal sync indication. Active high, extends from EAV to SAV for component video,
indicates TRS-ID location for composite video.
37 V BLANK O Vertical blanking interval indication. Active high during this period.
40-42 F0/HD1 O Field or standard indication pins. Field signals output when FIELD/STD pin is high, Video
F1/D1_D2, standard when FIELD/STD is low.
F2/NTSC_PAL
43,44 FL1,FL0 O Error Flag Status. Active high outputs programmed via S0, S1 to indicate various
transmission and hardware related error flags. Output flags stay active for one field.
17,39 V
DD
P Power Supply. Most positive power supply connection. (+5V)
18,38 V
SS
P Power Supply. Most negative power supply connection. (GND)
GS9001 PIN DESCRIPTIONS
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GS9001 - DETAILED DEVICE DESCRIPTION.
The GS9001 contains all functional blocks required to implement
Error Detection and Handling according to SMPTE RP165. It
also provides Field, Vertical, and Horizontal timing information
as well as Ancillary Data and TRS-ID indication. The device
offers standard independent operation and an I
2
C serial
communications interface to allow reading/writing of error
flags, device configuration and video standards format. The
device can also be operated in stand alone mode without the
I
2
C interface with error flags available on dedicated output
pins. In all modes, the device latency is four clock cycles.
Automatic Standards Detection
This block analyses the incoming 8 or 10 bit data to determine
whether it is component or composite. In total, six standards
are automatically detected. For composite data conforming to
SMPTE 259M, the Timing Reference Signal and Identification
(TRS-ID) packet contains line and field information used to
detect the format. For component data conforming to SMPTE
125M, the TRS-ID packets for End of Active Video (EAV)and
Start of Active Video (SAV) are used to determine the format.
The TRS information is then used to determine whether the
composite signal is NTSC or PAL, or whether the component
signal has 13.5 MHz or 18 MHz luminance samples.
Noise immunity has also been included, to ensure that
momentary signal interruption does not affect the auto-
standards detection function. This built in noise immunity
results in delayed switching time between standards. Delays
range from as little as eight lines when switching between
component standards to as much as four frames when switching
between PAL and NTSC composite standards. The latter
delay is due to the method used to differentiate PAL and NTSC,
which counts the number of lines per frame and requires four
sequential frames before switching standards. Manual override
of the auto-standard feature is provided via the I
2
C interface,
for applications where the standards recognition delay is
intolerable. Standards indication is provided on multiplexed
output pins or via the I
2
C interface.
Control Logic
The control logic coordinates operation and extracts timing
signals such as vertical blanking, horizontal sync, field ID,
ancillary data indication and TRS-ID indication.
The vertical blanking interval signal is active during the digital
vertical blanking period for all signal formats. The horizontal
sync signal is provided as a pulse with a duration of one clock
period for every TRS-ID occurrence in composite video. For
component video, the horizontal sync is a positive going pulse
which starts at EAV and ends at SAV. Three field ID bits (pins
40, 41, 42) indicate the two fields for component video standards,
the four colour fields for composite NTSC or eight colour fields
for composite PAL.
The ancillary data indication allows external circuitry to identify
ancillary data in the data stream for extraction or masking.
The presence of ancillary data is indicated by a logic high that
extends from the Data ID word to the Checksum word of each
ancillary packet. These timing signals are available on
dedicated output pins and through the I
2
C communications
interface.
The control logic also verifies incoming data validity by checking
the occurrence of consecutive TRS-IDs. If the absence of
seven consecutive TRS-IDs is detected, a “NO TRS” flag is
output on pin 34. This flag is reset once seven consecutive
TRS-IDs occur.
CRC Calculation
A cyclic redundancy check (CRC) is calculated for each video
field according to the CRC-CCITT polynomial X
16
+X
12
+X
5
+1.
Separate CRCs are calculated for active picture and full field
to provide an indication that active video is still intact despite
possible full field errors. This allows the user to distinguish
between different classes of data errors, which yields the best
compromise in error detection for all types of equipment. In
order to provide compatibility between 8 bit and 10 bit systems,
all data words with values between 3FC
H
and 3FF
H
inclusive,
are recoded as 3FF
H
at the input of the polynomial generator.
Start and end points for the CRC calculation are as defined in
RP165 and depend on the standard and check field being
calculated. Calculated CRC words can be read through the
I
2
C interface.
CRC Comparison
The GS9001 can be configured for transmit or receive mode.
In receive mode, the calculated CRC is checked against the
incoming CRC embedded in the error data packet. Any
mismatch will generate status error flags to indicate transmission
related error flags in either active picture, full field or both. The
error flags resulting from CRC mismatch are full field error
detected here (
EDH
) and active picture
EDH
.
Ancillary Checksum Verification
The ancillary data checksums are also verified to ensure data
integrity. Ancillary data is preceded by the Data Header, Data
ID, Block Number and Data Count. The Data Count shows the
number of ancillary words contained in each ancillary data
packet. A checksum is calculated for each incoming ancillary
data packet and compared with the transmitted checksum.
Any difference is reported as an error via the ancillary
EDH
error flag. A separate
ANC EXT
error flag is also provided to
indicate corruption of the EDH data packet.
Error Flags and Formatting
This block performs the functions of error flag reporting and
recoding, EDH data packet construction, programmable
interrupt generation and interface with the I
2
C communication
block.
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7.
UES
for AP, FF and Ancillary
UES
is set if the incoming
UES
is set. Also,
if the incoming data does not have an error data
packet, this flag is set. This is to inform the down-
stream devices that the data being sent has not
been previously checked for data errors.
In addition to error flag access through the I
2
C interface,
selected
EDH, EDA, IDH, IDA
and
UES
flags are available on
two user programmable output pins. Table 2 (on page 3)
shows these error flags and the corresponding input addresses.
These flags are available for applications where access to the
I
2
C interface via microcontroller is not possible or cost effective.
These flags give the user immediate warning of transmission
related errors either locally or from upstream equipment.
In situations where the upstream equipment does not support
EDH, a new error data packet is inserted in the data stream as
specified in RP165. In this case the
UES
flag is set for active
picture, full field and ancillary data. The
EDH
,
EDA
and
IDA
flags are reset for active picture and full field. For ancillary
data, the
EDH
flag is still reported if there are any checksum
errors and the
EDA
and
IDA
flags are reset. This is done since
the checksums for ancillary data may still be valid without the
presence of an error data packet in the data stream.
Transmit vs Receive Modes
The preceding description refers to the device in Receive
mode. In Transmit mode, valid CRC-check words for active
picture and full field are inserted and all error flags are reset.
Flag Masking
Any of the fifteen error flags can be set/reset or made transparent
using the I
2
C interface. Transparent flags are updated on the
occurrence of data errors. Flag masking can be done only
when the device is in the receive mode. During transmit mode
all error flags are reset. The transmit mode would be used for
source equipment and equipment that modifies or processes
the data before re-serializing.
Programmable Interrupt
The interrupt output can be made sensitive to any specific or
all error flags. This function is programmed using the sensitivity
flags SANC, SFF and SAP as described in the section for I
2
C
interface WRITE format.
Errored Field Counter
This 21 bit counter can be used to count the number of fields
in which data errors occur. The same set of sensitivity flags
used for the programmable interrupt, also control the
incrementing of this counter. This counter can be made to
increment on the occurrence of any specific type of error flag
in a field.
Error Reporting
Error reporting is meant to provide the information necessary
to allow system diagnostics. There are fifteen error flags in
total, which are used to identify specific error types. All flags
are available to be read or overwritten via the I
2
C interface.
The definition of these flags and an explanation of how the
device handles these flags are described below.
The acronyms used are:
EDA
Error Detected Already
EDH
Error Detected Here
IDH
Internal device error Detected Here
IDA
Internal device error Detected Already
UES
Unknown Error Status
AP
Active Picture
FF
Full Field
1.
EDH
for AP and FF
If the incoming CRC checkword is different from the
calculated CRC checkword, the
EDH
flag is set.
2.
EDH
for Ancillary
If the checksum for the ancillary data does not match
the calculated checksum, this flag is set.
3.
EDA
for AP and FF
This flag is generated by summing the incoming
EDA
flag with the product of the incoming
EDH
flag and the valid CRC bit. As a result, if the
incoming
EDH
flag is set and the
EDA
flag has not
been set, the
EDH
flag will be recoded to
EDA
and
then cleared. If the incoming CRC is invalid, then the
outgoing
EDA
flag will be determined by the incoming
EDA
flag only. This is to support devices in the
transmission path that do not generate valid CRC,yet
pass only the
EDA
flags.
4.
EDA
for Ancillary
This flag is the sum of the in-coming
EDH
and
EDA
flags for ancillary data.
5.
IDH
for AP, FF and Ancillary
These flags are set by the user through the I
2
C
serial interface. They can be used to indicate any
internal device errors in the vicinity of the device.
Examples could be local hardware errors such as
a RAM failure or a system diagnostics failure on power-
up.
6.
IDA
for AP, FF and Ancillary
This flag is the sum of the incoming
IDH
and
IDA
flags
for AP, FF and ancillary data.

GS9001-CQME3

Mfr. #:
Manufacturer:
Semtech
Description:
Specialty Function Logic PQFP 44pin (96/tray)
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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