© 2002 Fairchild Semiconductor Corporation DS005968 www.fairchildsemi.com
October 1987
Revised March 2002
CD4046BC Micropower Phase-Locked Loop
CD4046BC
Micropower Phase-Locked Loop
General Description
The CD4046BC micropower phase-locked loop (PLL) con-
sists of a low power, linear, voltage-controlled oscillator
(VCO), a source follower, a zener diode, and two phase
comparators. The two phase comparators have a common
signal input and a common comparator input. The signal
input can be directly coupled for a large voltage signal, or
capacitively coupled to the self-biasing amplifier at the sig-
nal input for a small voltage signal.
Phase comparator I, an exclusive OR gate, provides a digi-
tal error signal (phase comp. I Out) and maintains 90
°
phase shifts at the VCO center frequency. Between signal
input and comparator input (both at 50% duty cycle), it may
lock onto the signal input frequencies that are close to har-
monics of the VCO center frequency.
Phase comparator II is an edge-controlled digital memory
network. It provides a digital error signal (phase comp. II
Out) and lock-in signal (phase pulses) to indicate a locked
condition and maintains a 0
° phase shift between signal
input and comparator input.
The linear voltage-controlled oscillator (VCO) produces an
output signal (VCO Out) whose frequency is determined by
the voltage at the VCO
IN
input, and the capacitor and resis-
tors connected to pin C1
A
, C1
B
, R1 and R2.
The source follower output of the VCO
IN
(demodulator Out)
is used with an external resistor of 10 k
or more.
The INHIBIT input, when high, disables the VCO and
source follower to minimize standby power consumption.
The zener diode is provided for power supply regulation, if
necessary.
Features
Wide supply voltage range: 3.0V to 18V
Low dynamic power consumption: 70
µW (typ.)
at f
o
= 10 kHz, V
DD
= 5V
VCO frequency: 1.3 MHz (typ.) at V
DD
= 10V
Low frequency drift: 0.06%/
°C at V
DD
= 10V with
temperature
High VCO linearity: 1% (typ.)
Applications
FM demodulator and modulator
Frequency synthesis and multiplication
Frequency discrimination
Data synchronization and conditioning
Voltage-to-frequency conversion
Tone decoding
FSK modulation
Motor speed control
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter X to the ordering code.
Order Number Package Number Package Description
CD4046BCM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
CD4046BCN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
www.fairchildsemi.com 2
CD4046BC
Connection Diagram
Top View
Block Diagram
FIGURE 1.
3 www.fairchildsemi.com
CD4046BC
Absolute Maximum Ratings(Note 1)
(Note 2)
Recommended Operating
Conditions
(Note 2)
Note 1: Absolute Maximum Ratings are those values beyond which the
safety of the device cannot be guaranteed. They are not meant to imply
that the devices should be operated at these limits. The table of Recom-
mended Operating Conditions and Electrical Characteristics provides
conditions for actual device operation.
Note 2: V
SS
= 0V unless otherwise specified.
DC Electrical Characteristics (Note 2)
Note 3: Capacitance is guaranteed by periodic testing.
Note 4: I
OH
and I
OL
are tested one output at a time.
DC Supply Voltage (V
DD
) 0.5 to +18 V
DC
Input Voltage (V
IN
) 0.5 to V
DD
+0.5 V
DC
Storage Temperature Range (T
S
) 65°C to +150°C
Power Dissipation (P
D
)
Dual-In-Line 700 mW
Small Outline 500 mW
Lead Temperature (T
L
)
(Soldering, 10 seconds) 260
°C
DC Supply Voltage (V
DD
) 3 to 15 V
DC
Input Voltage (V
IN
) 0 to V
DD
V
DC
Operating Temperature Range (T
A
) 55°C to +125°C
Symbol Parameter Conditions
55°C +25°C +125°C
Units
Min Max Min Typ Max Min Max
I
DD
Quiescent Device Current Pin 5 = V
DD,
Pin 14 = V
DD,
Pin 3, 9 = V
SS
V
DD
= 5V 5 0.005 5 150
µAV
DD
= 10V 10 0.01 10 300
V
DD
= 15V 20 0.015 20 600
Pin 5 = V
DD
, Pin 14 = Open,
Pin 3, 9 = V
SS
V
DD
= 5V 45 5 35 185
µAV
DD
= 10V 450 20 350 650
V
DD
= 15V 1200 50 900 1500
V
OL
LOW Level Output Voltage V
DD
= 5V 0.05 0 0.05 0.05
VV
DD
= 10V 0.05 0 0.05 0.05
V
DD
= 15V 0.05 0 0.05 0.05
V
OH
HIGH Level Output Voltage V
DD
= 5V 4.95 4.95 5 4.95
VV
DD
= 10V 9.95 9.95 10 9.95
V
DD
= 15V 14.95 14.95 15 14.95
V
IL
LOW Level Input Voltage V
DD
= 5V, V
O
= 0.5V or 4.5V 1.5 2.25 1.5 1.5
VComparator and Signal In V
DD
= 10V, V
O
= 1V or 9V 3.0 4.5 3.0 3.0
V
DD
= 15V, V
O
= 1.5V or 13.5V 4.0 6.25 4.0 4.0
V
IH
HIGH Level Input Voltage V
DD
= 5V, V
O
= 0.5V or 4.5V 3.5 3.5 2.75 3.5
VComparator and Signal In V
DD
= 10V, V
O
= 1V or 9V 7.0 7.0 5.5 7.0
V
DD
= 15V, V
O
= 1.5V or 13.5V 11.0 11.0 8.25 11.0
I
OL
LOW Level Output Current V
DD
= 5V, V
O
= 0.4V 0.64 0.51 0.88 0.36
mA(Note 4) V
DD
= 10V, V
O
= 0.5V 1.6 1.3 2.25 0.9
V
DD
= 15V, V
O
= 1.5V 4.2 3.4 8.8 2.4
I
OH
HIGH Level Output Current V
DD
= 5V, V
O
= 4.6V 0.64 0.51 0.88 0.36
mA(Note 4) V
DD
= 10V, V
O
= 9.5V 1.6 1.3 2.25 0.9
V
DD
= 15V, V
O
= 13.5V 4.2 3.4 8.8 2.4
I
IN
Input Current All Inputs Except Signal Input
V
DD
= 15V, V
IN
= 0V 0.1 10
5
0.1 1.0
µA
V
DD
= 15V, V
IN
= 15V 0.1 10
5
0.1 1.0
C
IN
Input Capacitance Any Input (Note 3) 7.5 pF
P
T
Total Power Dissipation f
o
= 10 kHz, R1 = 1 M,
R2 = ∞, VCO
IN
= V
CC
/2
V
DD
= 5V 0.07
mWV
DD
= 10V 0.6
V
DD
= 15V 2.4

CD4046BCM

Mfr. #:
Manufacturer:
ON Semiconductor / Fairchild
Description:
Phase Locked Loops - PLL Phase-Locked Loop
Lifecycle:
New from this manufacturer.
Delivery:
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