22
LTC3808
3808f
APPLICATIO S I FOR ATIO
WUUU
Checking Transient Response
The regulator loop response can be checked by looking at
the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, V
OUT
immediately shifts by an amount
equal to (∆I
LOAD
) • (ESR), where ESR is the effective series
resistance of C
OUT
. ∆I
LOAD
also begins to charge or
discharge C
OUT
generating a feedback error signal used by
the regulator to return V
OUT
to its steady-state value.
During this recovery time, V
OUT
can be monitored for
overshoot or ringing that would indicate a stability prob-
lem. OPTI-LOOP compensation allows the transient re-
sponse to be optimized over a wide range of output
capacitance and ESR values.
The I
TH
series R
C
-C
C
filter (see Functional Diagram) sets
the dominant pole-zero loop compensation.
The I
TH
external components showed in the figure on the
first page of this data sheet will provide adequate compen-
sation for most applications. The values can be modified
slightly (from 0.2 to 5 times their suggested values) to
optimize transient response once the final PC layout is
done and the particular output capacitor type and value
have been determined. The output capacitor needs to be
decided upon because the various types and values deter-
mine the loop feedback factor gain and phase. An output
current pulse of 20% to 100% of full load current having
a rise time of 1µs to 10µs will produce output voltage and
I
TH
pin waveforms that will give a sense of the overall loop
stability. The gain of the loop will be increased by increas-
ing R
C
and the bandwidth of the loop will be increased by
decreasing C
C
. The output voltage settling behavior is
related to the stability of the closed-loop system and will
demonstrate the actual overall supply performance. For a
detailed explanation of optimizing the compensation com-
ponents, including a review of control loop theory, refer to
Application Note 76.
A second, more severe transient is caused by switching in
loads with large (>1µF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with C
OUT
, causing a rapid drop in V
OUT
. No regulator can
deliver enough current to prevent this problem if the load
switch resistance is low and it is driven quickly. The only
solution is to limit the rise time of the switch drive so that
the load rise time is limited to approximately (25) •
(C
LOAD
). Thus a 10µF capacitor would be require a 250µs
rise time, limiting the charging current to about 200mA.
Design Example
As a design example, assume V
IN
will be operating from a
maximum of 4.2V down to a minimum of 2.75V (powered
by a single lithium-ion battery). Load current requirement
is a maximum of 2A, but most of the time it will be in a
standby mode requiring only 2mA. Efficiency at both low
and high load currents is important. Burst Mode operation
at light loads is desired. Output voltage is 1.8V. The IPRG
pin will be left floating, so the maximum current sense
threshold ∆V
SENSE(MAX)
is approximately 125mV.
MaximumDuty Cycle
V
V
OUT
IN MIN
=
()
.%= 65 5
From Figure 1, SF = 82%.
RSF
V
I
DS ON MAX
SENSE MAX
OUT MAX T
()
()
()
•.• •
•
.=
∆
= Ω
5
6
09 0032
ρ
A 0.032Ω P-channel MOSFET in Si7540DP is close to this
value.
