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LTC3548IMSE#PBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
LTC3548
13
3548fc
Low Ripple Buck Regulators Using Ceramic Capacitors
RUN2 V
IN
V
IN
= 2.5V
TO 5.5V
V
OUT2
= 1.8V
AT 400mA
V
OUT1
= 1.2V
AT 800mA
RUN1
POR
SW1
V
FB1
GND
V
FB2
SW2
MODE/SYNC
LTC3548
C1
10μF
R5
100k
POWER-ON
RESET
C4, 33pFC5, 68pF
L1
4.7μH
L2
10μH
R4
887k
R2
604k
R1
604k
R3
442k
C3
10μF
C2
10μF
3548 TA03
C1, C2, C3: TDK C2012X5R0J106M L1: SUMIDA CDRH2D18/HP-4R7NC
L2: SUMIDA CDRH2D18/HP-100NC
LOAD CURRENT (mA)
EFFICIENCY (%)
10 100 1000
3548 TA03b
100
95
90
85
80
75
70
65
60
55
50
1.8V
1.2V
V
IN
= 3.3V
PULSE SKIP MODE
NO LOAD ON OTHER CHANNEL
Effi ciency vs Load Current
Figure 4. LTC3548 Layout Diagram (See Board Layout Checklist)
RUN2 V
IN
V
IN
V
OUT2
V
OUT1
RUN1
POR
SW1
V
FB1
GND
V
FB2
SW2
MODE/SYNC
LTC3548
C
IN
C4C5
L1
L2
R4 R2
R1
R3
C
OUT2
C
OUT1
3548 F04
BOLD LINES INDICATE HIGH CURRENT PATHS
RUN2 V
IN
V
IN
= 2.5V*
TO 5.5V
V
OUT2
= 2.5V*
AT 400mA
V
OUT1
= 1.8V
AT 800mA
RUN1
POR
SW1
V
FB1
GND
V
FB2
SW2
MODE/SYNC
LTC3548
C1
10μF
R5
100k
POWER-ON
RESET
C4, 33pF
C5, 68pF
L1
2.2μH
L2
4.7μH
R4
887k
R2
604k
R1
301k
R3
280k
C3
4.7μF
C2
10μF
3548 F03
C1, C2, C3: TAIYO YUDEN JMK212BJ106MG
C3: TAIYO YUDEN JMK212BJ475MG
L1: MURATA LQH32CN2R2M11
L2: MURATA LQH32CN4R7M23
*V
OUT
CONNECTED TO V
IN
FOR V
IN
≤ 2.8V (DROPOUT)
Figure 3. LTC3548 Typical Application
APPLICATIONS INFORMATION
TYPICAL APPLICATIONS
LTC3548
14
3548fc
TYPICAL APPLICATIONS
RUN2 V
IN
V
IN
= 3.6V
TO 5.5V
V
OUT2
= 3.3V
AT 400mA
V
OUT1
= 1.8V
AT 800mA
RUN1
POR
SW1
V
FB1
GND
V
FB2
SW2
MODE/SYNC
LTC3548
C1*
10μF
R5
100k
POWER-ON
RESET
C4, 33pFC5, 68pF
L1
2.2μH
L2
4.7μH
R4
887k
R2
604k
R1
301k
R3
196k
C3
4.7μF
C2
10μF
3548 TA07
C1, C2: MURATA GRM219R60J106KE19
C3: MURATA GRM219R60J475KE19
L1: COILTRONICS LPO3310-222MX
L2: COILTRONICS LPO3310-472MX
*IF C1 IS GREATER THAN 3" FROM POWER SOURCE,
ADDITIONAL CAPACITANCE MAY BE REQUIRED.
1mm Profi le Core and I/O Supplies
Effi ciency vs Load Current
LOAD CURRENT (mA)
1
EFFICIENCY (%)
100
95
90
85
80
75
70
65
60
10 100 1000
3548 TA08
3.3V
1.8V
V
IN
= 5V
Burst Mode OPERATION
NO LOAD ON OTHER CHANNEL
DD Package
10-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1699 Rev B)
3.00 p0.10
(4 SIDES)
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION
OF (WEED-2). CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT
STATUS OF VARIATION ASSIGNMENT
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
0.40 p 0.10
BOTTOM VIEW—EXPOSED PAD
1.65 p 0.10
(2 SIDES)
0.75 p0.05
R = 0.125
TYP
2.38 p0.10
(2 SIDES)
15
106
PIN 1
TOP MARK
(SEE NOTE 6)
0.200 REF
0.00 – 0.05
(DD) DFN REV B 0309
0.25 p 0.05
2.38 p0.05
(2 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
1.65 p0.05
(2 SIDES)2.15 p0.05
0.50
BSC
0.70 p0.05
3.55 p0.05
PACKAGE
OUTLINE
0.25 p 0.05
0.50 BSC
PACKAGE DESCRIPTION
LTC3548
15
3548fc
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
PACKAGE DESCRIPTION
MSE Package
10-Lead Plastic MSOP, Exposed Die Pad
(Reference LTC DWG # 05-08-1664 Rev C)
MSOP (MSE) 0908 REV C
0.53 p 0.152
(.021 p .006)
SEATING
PLANE
0.18
(.007)
1.10
(.043)
MAX
0.17 – 0.27
(.007 – .011)
TYP
0.86
(.034)
REF
0.50
(.0197)
BSC
12
3
45
4.90 p 0.152
(.193 p .006)
0.497 p 0.076
(.0196 p .003)
REF
8910
10
1
7
6
3.00 p 0.102
(.118 p .004)
(NOTE 3)
3.00 p 0.102
(.118 p .004)
(NOTE 4)
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.254
(.010)
0
o – 6o TYP
DETAIL “A”
DETAIL “A”
GAUGE PLANE
5.23
(.206)
MIN
3.20 – 3.45
(.126 – .136)
0.889 p 0.127
(.035 p .005)
RECOMMENDED SOLDER PAD LAYOUT
0.305 p 0.038
(.0120 p .0015)
TYP
2.083 p 0.102
(.082 p .004)
2.794 p 0.102
(.110 p .004)
0.50
(.0197)
BSC
BOTTOM VIEW OF
EXPOSED PAD OPTION
1.83 p 0.102
(.072 p .004)
2.06 p 0.102
(.081 p .004)
0.1016 p 0.0508
(.004 p .002)
DETAIL “B”
DETAIL “B”
CORNER TAIL IS PART OF
THE LEADFRAME FEATURE.
FOR REFERENCE ONLY
NO MEASUREMENT PURPOSE
0.05 REF
0.29
REF
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LTC3548IMSE#PBF

Mfr. #:
Buy LTC3548IMSE#PBF
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators Dual, Sync. 800mA/400mA, 2.25MHz Step Down in DFN
Lifecycle:
New from this manufacturer.
Delivery:
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