74ACTQ16245SSC

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74ACTQ16245
AC Electrical Characteristics
Note 8: Voltage Range 5.0 is 5.0V 0.5V.
Extended AC Electrical Characteristics
Note 9: Voltage Range 5.0 is 5.0V 0.5V.
Note 10: Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device.
The specification applies to any outputs switching HIGH-to-LOW (t
OSHL
), LOW-to-HIGH (t
OSLH
), or any combination switching LOW-to-HIGH and/or HIGH-
to-LOW (t
OST
).
Note 11: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.).
Note 12: This specification is guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load
capacitors in the standard AC load. This specification pertains to single output switching only.
Note 13: 3-STATE delays are load dominated and have been excluded from the datasheet.
Note 14: The Output Disable Time is dominated by the RC network (500
, 250 pF) on the output and has been excluded from the datasheet.
Capacitance
V
CC
T
A
25 CT
A
40 C to 85 C
Symbol Parameter (V)
C
L
50 pF C
L
50 pF
Units
(Note 8) Min Typ Max Min Max
t
PLH
Propagation Delay 5.0 3.2 5.7 8.4 3.2 9.0
ns
t
PHL
A
n
, B
n
to B
n
, A
n
5.02.65.17.92.68.4
t
PZH
Output Enable 5.0 3.7 6.4 9.4 2.7 10.0
ns
t
PZL
Time 5.0 4.1 7.4 10.5 3.4 11.6
t
PHZ
Output Disable 5.0 2.2 5.4 8.7 2.2 9.3
ns
t
PLZ
Time 5.02.05.28.22.08.8
T
A
40 C to 85 C
C
L
50 pF T
A
40 C to 85 C
Symbol Parameter
V
CC
16 Outputs Switching
C
L
250 pF
Units
(V) (Note 11) (Note 12)
(Note 9) Min Typ Max Min Max
t
PLH
Propagation Delay 5.0 4.2 11.9 5.9 14.6
ns
t
PHL
Data to Output 5.0 3.5 9.9 5.0 13.4
t
PZH
Output Enable Time 5.0 4.5 11.4
(Note 13) ns
t
PZL
5.0 4.4 12.2
t
PHZ
Output Disable Time 5.0 3.5 9.3
(Note 14) ns
t
PZL
5.0 3.1 8.8
t
OSHL
Pin to Pin Skew 5.0 1.2 ns
(Note 10) HL Data to Output
t
OSLH
Pin to Pin Skew 5.0 1.3 ns
(Note 10) LH Data to Output
t
OST
Pin to Pin Skew 5.0 3.0 ns
(Note 10) LH/HL Data to Output
Symbol Parameter Typ Units Conditions
C
IN
Input Pin Capacitance 4.5 pF V
CC
5.0V
C
PD
Power Dissipation Capacitance 25 pF V
CC
5.0V
5 www.fairchildsemi.com
74ACTQ16245
FACT Noise Characteristics
The setup of a noise characteristics measurement is critical
to the accuracy and repeatability of the tests. The following
is a brief description of the setup used to measure the
noise characteristics of FACT.
Equipment:
Hewlett Packard Model 8180A Word Generator
PC-163A Test Fixture
Tektronics Model 7854 Oscilloscope
Procedure:
1. Verify Test Fixture Loading: Standard Load 50 pF,
500
.
2. Deskew the HFS generator so that no two channels
have greater than 150 ps skew between them. This
requires that the oscilloscope be deskewed first. It is
important to deskew the HFS generator channels
before testing. This will ensure that the outputs switch
simultaneously.
3. Terminate all inputs and outputs to ensure proper load-
ing of the outputs and that the input levels are at the
correct voltage.
4. Set the HFS generator to toggle all but one output at a
frequency of 1 MHz. Greater frequencies will increase
DUT heating and effect the results of the measure-
ment.
V
OHV
and V
OLP
are measured with respect to ground reference.
Input pulses have the following characteristics: f
1MHz, t
r
3ns,
t
f
3 ns, skew 150 ps.
FIGURE 1. Quiet Output Noise Voltage Waveforms
5. Set the HFS generator input levels at 0V LOW and 3V
HIGH for ACT devices and 0V LOW and 5V HIGH for
AC devices. Verify levels with an oscilloscope.
V
OLP
/V
OLV
and V
OHP
/V
OHV
:
Determine the quiet output pin that demonstrates the
greatest noise levels. The worst case pin will usually be
the furthest from the ground pin. Monitor the output volt-
ages using a 50
coaxial cable plugged into a standard
SMB type connector on the test fixture. Do not use an
active FET probe.
Measure V
OLP
and V
OLV
on the quiet output during the
worst case transition for active and enable. Measure
V
OHP
and V
OHV
on the quiet output during the worst
case active and enable transition.
Verify that the GND reference recorded on the oscillo-
scope has not drifted to ensure the accuracy and repeat-
ability of the measurements.
V
ILD
and V
IHD
:
Monitor one of the switching outputs using a 50
coaxial
cable plugged into a standard SMB type connector on
the test fixture. Do not use an active FET probe.
First increase the input LOW voltage level, V
IL
, until the
output begins to oscillate or steps out a min of 2 ns.
Oscillation is defined as noise on the output LOW level
that exceeds V
IL
limits, or on output HIGH levels that
exceed V
IH
limits. The input LOW voltage level at which
oscillation occurs is defined as V
ILD
.
Next decrease the input HIGH voltage level, V
IH
, until
the output begins to oscillate or steps out a min of 2 ns.
Oscillation is defined as noise on the output LOW level
that exceeds V
IL
limits, or on output HIGH levels that
exceed V
IH
limits. The input HIGH voltage level at which
oscillation occurs is defined as V
IHD
.
Verify that the GND reference recorded on the oscillo-
scope has not drifted to ensure the accuracy and repeat-
ability of the measurements.
FIGURE 2. Simultaneous Switching Test Circuit
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74ACTQ16245
Physical Dimensions inches (millimeters) unless otherwise noted
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
Package Number MS48A

74ACTQ16245SSC

Mfr. #:
Manufacturer:
ON Semiconductor / Fairchild
Description:
Bus Transceivers 16-Bit Transceiver
Lifecycle:
New from this manufacturer.
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