DS1808
14 of 17
NOTES:
1. All voltages are referenced to ground.
2. I/O pins of fast mode devices must not obstruct the SDA and SCL lines if V
CC
is switched off.
3. The value of V
DD
should never exceed V
CC
, including during power-ups. V
CC
must be applied before
either V
DD
or V
B
. V
DD
and V
B
can then follow in any order.
4. I
STBY
specified for V
DD
equal to 5.0V. Control port logic pins are driven to the appropriate logic
levels. Appropriate logic levels specify that logic inputs are within a 0.5V of ground or V
DD
for the
corresponding inactive state.
5. A fast mode device can be used in a standard mode system, but the requirement t
SU:DAT
> 250ns
must then be met. This will automatically be the case if the device does not stretch the LOW period of
the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the
next data bit to the SDA line t
RMAX
+ t
SU:DAT
= 1000 + 250 = 1250ns before the SCL line is
released.
6. After this period, the first clock pulse is generated.
7. The maximum t
HD:DAT
has only to be met if the device does not stretch the LOW period (t
LOW
) of
the SCL signal.
8. C
B
– Total capacitance of one bus line in picofarads, timing referenced to (0.9)(V
DD
) and (0.1)(V
DD
).
9. Absolute linearity is used to measure expected wiper voltage as determined by wiper position.
10. Relative linearity is used to determine the change of wiper voltage between two adjacent wiper
positions.
11. When used as a rheostat or variable resistor the resistance temperature coefficient is: 750ppm/°C.
When used as a voltage divider or potentiometer, the output voltage temperature coefficient
approaches 30 ppm/°C.
12. I
CC
specified with SDA pin open.
13. Maximum I
CC
is dependent on clock rates.
