9
LTC3832/LTC3832-1
sn3832 3832fs
APPLICATIO S I FOR ATIO
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Also included in the LTC3832 is an internal soft-start
feature that requires only a single external capacitor to
operate. In addition, the LTC3832 features an adjustable
oscillator that can free run or synchronize to external
signal with frequencies from 100kHz to 500kHz, allowing
added flexibility in external component selection. The
LTC3832-1 does not include current limit, frequency
adjustability, external synchronization and the shutdown
function.
THEORY OF OPERATION
Primary Feedback Loop
The LTC3832/LTC3832-1 sense the output voltage of the
circuit at the output capacitor and feeds this voltage back
to the internal transconductance error amplifier, ERR,
through a resistor divider network. The error amplifier
compares the resistor-divided output voltage to the inter-
nal 0.6V reference and outputs an error signal to the PWM
comparator. This error signal is compared with a fixed
frequency ramp waveform, from the internal oscillator, to
generate a pulse width modulated signal. This PWM signal
drives the external MOSFETs through the G1 and G2 pins.
The resulting chopped waveform is filtered by L
O
and C
OUT
which closes the loop. Loop compensation is achieved
with an external compensation network at the COMP pin,
the output node of the error amplifier.
MAX Feedback Loop
An additional comparator in the feedback loop provides
high speed output voltage correction in situations where
the error amplifier may not respond quickly enough. MAX
compares the feedback signal to a voltage 60mV above the
internal reference. If the signal is above the comparator
threshold, the MAX comparator overrides the error ampli-
fier and forces the loop to minimum duty cycle, 0%. To
prevent this comparator from triggering due to noise, the
MAX comparator’s response time is deliberately delayed
by two to three microseconds. This comparator helps
prevent extreme output perturbations with fast output
load current transients, while allowing the main feedback
loop to be optimally compensated for stability.
Thermal Shutdown
The LTC3832/LTC3832-1 have a thermal protection cir-
cuit that disables both gate drivers if activated. If the chip
junction temperature reaches 150°C, both G1 and G2 are
pulled low. G1 and G2 remain low until the junction
temperature drops below 125°C, after which, the chip
resumes normal operation.
Soft-Start and Current Limit
The LTC3832 includes a soft-start circuit that is used for
start-up and current limit operation. The LTC3832-1 only
has the soft-start function; the current limit function is
disabled. The SS pin requires an external capacitor, C
SS
,
to GND with the value determined by the required soft-
start time. An internal 12µA current source is included to
charge C
SS
. During power-up, the COMP pin is clamped to
a diode drop (B-E junction of QSS in the Block Diagram)
above the voltage at the SS pin. This prevents the error
amplifier from forcing the loop to maximum duty cycle.
The LTC3832/LTC3832-1 operate at low duty cycle as the
SS pin rises above 0.6V (V
COMP
≈ 1.2V). As SS continues
to rise, QSS turns off and the error amplifier takes over to
regulate the output.
The LTC3832 includes yet another feedback loop to con-
trol operation in current limit. Just before every falling
edge of G1, the current comparator, CC, samples and
holds the voltage drop measured across the external
upper MOSFET, Q1, at the I
FB
pin. CC compares the voltage
at I
FB
to the voltage at the I
MAX
pin. As the peak current
rises, the measured voltage across Q1 increases due to the
drop across the R
DS(ON)
of Q1. When the voltage at I
FB
drops below I
MAX
, indicating that Q1’s drain current has
exceeded the maximum level, CC starts to pull current out
of C
SS
, cutting the duty cycle and controlling the output
current level. The CC comparator pulls current out of the
SS pin in proportion to the voltage difference between I
FB
and I
MAX
. Under minor overload conditions, the SS pin
falls gradually, creating a time delay before current limit
takes effect. Very short, mild overloads may not affect the
output voltage at all. More significant overload conditions
allow the SS pin to reach a steady state, and the output
