Operation modes M48Z2M1Y, M48Z2M1V
10/20 Doc ID 5135 Rev 6
Table 4. WRITE mode AC characteristics
2.3 Data retention mode
With valid V
CC
applied, the M48Z2M1Y/V operates as a conventional BYTEWIDE™ static
RAM. Should the supply voltage decay, the RAM will automatically power-fail deselect, write
protecting itself t
WP
after V
CC
falls below V
PFD
. All outputs become high impedance, and all
inputs are treated as “Don't care.”
If power fail detection occurs during a valid access, the memory cycle continues to
completion. If the memory cycle fails to terminate within the time t
WP
, write protection takes
place. When V
CC
drops below V
SO
, the control circuit switches power to the internal energy
source which preserves data.
The internal coin cells will maintain data in the M48Z2M1Y/V after the initial application of
V
CC
for an accumulated period of at least 10 years when V
CC
is less than V
SO
. As system
power returns and V
CC
rises above V
SO
, the batteries are disconnected, and the power
supply is switched to external V
CC
. Write protection continues for t
ER
after V
CC
reaches
V
PFD
to allow for processor stabilization. After t
ER
, normal RAM operation can resume.
For more information on battery storage life refer to the application note AN1012.
Symbol Parameter
(1)
1. Valid for ambient operating temperature: T
A
= 0 to 70 °C; V
CC
= 4.5 to 5.5 V or 3.0 to 3.6V (except where
noted).
M48Z2M1Y M48Z2M1V
Unit–70 –85
Min Max Min Max
t
AVAV
WRITE cycle time 70 85 ns
t
AVEH
Address valid to chip enable high 65 75 ns
t
AVEL
Address valid to chip enable low 0 0 ns
t
AVWH
Address valid to WRITE enable high 65 75 ns
t
AVWL
Address valid to WRITE enable low 0 0 ns
t
DVEH
Input valid to chip enable high 30 35 ns
t
DVWH
Input valid to WRITE enable high 30 35 ns
t
EHAX
Chip enable high to address transition 15 15 ns
t
EHDX
Chip enable high to input transition 10 15 ns
t
ELEH
Chip enable low to chip enable high 55 75 ns
t
WHAX
WRITE enable high to address transition 5 5 ns
t
WHDX
WRITE enable high to input transition 0 0 ns
t
WHQX
(2)(3)
2. C
L
= 5 pF (see Figure 9 on page 13).
3. If E
goes low simultaneously with W going low, the outputs remain in the high impedance state.
WRITE enable high to output transition 5 5 ns
t
WLQZ
(2)(3)
WRITE enable low to output Hi-Z 25 30 ns
t
WLWH
WRITE enable pulse width 55 65 ns
Obsolete Product(s) - Obsolete Product(s)
