74HC4538D
6
12.
12.
12.
12. Functional Description
Functional Description
Functional Description
Functional Description
(1) Stand-by state
The external capacitor is fully charge to V
CC
in the stand-by state. That means, before triggering, Q
P
and Q
N
transistors which are connected to the T2 node are in the off state. Two comparators that relate
to the timing of the output pulse, and two reference voltage supplies stop their operation. The total
supply current is only leakage current.
(2) Trigger operation
Trigger operation is effective in either of the following two cases. One is the condition where the A input
is low, and the B input has a falling signal. The other, where the B input is high, and the A input has a
rising signal.
After trigger becomes effective, comparators C
1
and C
2
start operating, and Q
N
is turned on. The
external capacitor discharges through Q
N
. The voltage level at the T2 node drops. If the T2 voltage level
falls to the internal reference voltage V
ref
L, the output of C
1
becomes low. The flip-flop is then reset and
Q
N
turns off. At that moment C
1
stops but C
2
continues operating.
After Q
N
turns off, the voltage at T2 start rising at a rate determined by the time constant of external
capacitor C
X
and resistor R
X
.
After the triggering, output Q becomes high, following some delay time of the internal F/F and gates. It
stays high even if the voltage of T2 changes from falling to rising. When T2 reaches the internal reference
voltage V
ref
H, the output of C
2
becomes low, the output Q goes low and C
2
stops its operation. That
means, after triggering, when the voltage level of T2 reaches V
ref
H, the IC returns to its MONOSTABLE
state.
In the case of large value of C
X
and R
X
, and ignoring the discharge time of the capacitor and internal
delays of the IC, the width of the output pulse, (t
wOUT
), is as follows:
t
wOUT
= 0.7 × C
X
× R
X
(3) Retrigger operation
When another new trigger is applied to input A or B while in the MONOSTABLE state, it is effective
only if the IC is charging C
X
. The voltage level of T2 then falls to V
ref
L level again.
Therefore the Q output stays high if the next trigger comes in before the time period set by C
X
and R
X
.
If the 2
nd
trigger is very close to previous trigger, such as application during the discharge cycle, the 2
nd
trigger will not be effective.
The minimum time for effective 2
nd
trigger, t
rr
(min), depends on V
CC
and C
X
.
(4) Reset operation
In normal operation, CD input is held high. If CD is low, a trigger has no effect because the Q output is
held low and the trigger control F/F is reset. Also, Q
P
turns on and C
X
is charged rapidly to V
CC
.
This means if CD input is set low, the IC goes into a wait state.
2017-01-24
Rev.6.0
©2016 Toshiba Corporation
