2003 Oct 21 25
Philips Semiconductors Product specification
Car radio integrated signal processor TEF6894H
Table 6 Description of data byte 1
11.1.2 DATA BYTE 2; LEVEL
Table 7 Format of data byte 2
Table 8 Description of data byte 2
BIT SYMBOL DESCRIPTION
7 STIN Stereo indicator. 0 = no pilot signal detected; 1 = pilot signal detected.
6 ASIA ASI active. 0 = not active; 1 = ASI step is in progress.
5 AFUS AF update sample. 0 = LEV, USN and WAM information is taken from main frequency
(continuous mode); 1 = LEV, USN and WAM information is taken from alternative
frequency. Continuous mode during AF update and sampled mode after AF update.
Sampled mode reverts to continuous main frequency information after read.
4 POR Power-on reset. 0 = standard operation (valid I
2
C-bus register settings); 1 = Power-on
reset detected since last read cycle (I
2
C-bus register reset). After read the bit will reset
to POR = 0.
3 Reserved.
2 to 0 ID[2:0] Identification. TEF6894H device type identification; ID[2:0] = 100.
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
LEV7 LEV6 LEV5 LEV4 LEV3 LEV2 LEV1 LEV0
BIT SYMBOL DESCRIPTION
7 to 0 LEV[7:0] Level. 8-bit value of level voltage from tuner; see Fig.4.
handbook, halfpage
05
V
LEVEL
(V)
V
eq
(V)
LEV
[
7:0
]
255
0
5
0
1
2
3
4
1234
MHC331
Fig.4 Equivalent level voltage V
eq
(MPH and LEV detector) as a function of level voltage V
LEVEL
.
2003 Oct 21 26
Philips Semiconductors Product specification
Car radio integrated signal processor TEF6894H
11.1.3 DATA BYTE 3; USN AND WAM
Table 9 Format of data byte 3
Table 10 Description of data byte 3
11.2 Write mode
Table 11 Format for subaddress byte with default setting
Table 12 Description of subaddress byte
Table 13 Selection of data byte
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
USN3 USN2 USN1 USN0 WAM3 WAM2 WAM1 WAM0
BIT SYMBOL DESCRIPTION
7 to 4 USN[3:0] Ultrasonic noise detector. USN content of the MPXRDS audio signal; see Fig.5.
3 to 0 WAM[3:0] Wideband AM detector. WAM content of the LEVEL voltage; see Fig.6.
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
AIOF GATE SGAT SA4 SA3 SA2 SA1 SA0
00−−−−−
BIT SYMBOL DESCRIPTION
7 AIOF Auto-increment off. 0 = auto-increment enabled; 1 = auto-increment disabled.
6GATEGate. 0=I
2
C-bus outputs (SDAG and SCLG) are controllable by the shortgate or the
autogate function; 1 = I
2
C-bus outputs are enabled.
5 SGAT Shortgate. 1=I
2
C-bus outputs (SDAG and SCLG) are enabled for a single
transmission following this control and disabled automatically.
4 to 0 SA[4:0] Data byte select. The subaddress value is auto-incremented when AIOF = 0 and will
revert from SA = 30 to SA = 0. SA = 31 can only be accessed via direct subaddress
selection, in which case auto-increment will revert from SA = 31 to SA = 0; see
Table 13.
SA4 SA3 SA2 SA1 SA0 HEX
(1)
MNEMONIC ADDRESSED DATA BYTE
000102RDSCLK test control
001004CONTROL control of supply and AF update
001015CSALIGN alignment of stereo channel separation
001106MULTIPATHcontrol of weak signal sensitivity and
timing
001117SNC alignment of SNC start and slope
010008HIGHCUT alignment of HCC start and slope
010019SOFTMUTE alignment soft mute start and slope
01010ARADIO control of radio functions
01011BINPUT/ASI input selector and ASI settings
01100CLOUDNESS loudness control
01101DVOLUME volume control
2003 Oct 21 27
Philips Semiconductors Product specification
Car radio integrated signal processor TEF6894H
Note
1. Data bytes 0, 1, 2 and 3 must not be used in the application. All bits in these bytes must be set to logic 0.
11.2.1 SUBADDRESS 2H; RDSCLK
Table 14 Format of data byte 2H with default setting
Table 15 Description of data byte 2H
11.2.2 S
UBADDRESS 4H; CONTROL
Table 16 Format of data byte 4H with default setting
Table 17 Description of data byte 4H
01110ETREBLE treble control
01111FBASS bass control
1000010FADER fader control
1000111BALANCE balance control
1001012MIX control of output mixer
1001113BEEP beep generator settings
111111FAUTOGATEautogate control
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
−−TST3 TST2 TST1 TST0 −−
−−0000−−
BIT SYMBOL DESCRIPTION
7 and 6 Not used. Set to logic 0.
5 to 2 TST[3:0] Test. TST[3:0] = 0000: normal operation.
1 and 0 Not used. Set to logic 0.
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
STBA AFUM AFUH RMUT LETF ATTB
100000
BIT SYMBOL DESCRIPTION
7 Not used. Set to logic 0.
6 STBA Standby mode audio processing. 0 = audio processing active; 1 = audio processing
in standby mode (audio inputs and outputs at DC).
5 AFUM Enables AF update mute. 0 = AF update mute disabled; 1 = AF update mute enabled
(controlled by AFSAMP and AFHOLD input).
4 AFUH AF update hold function. 0 = disable, the weak signal processing hold is controlled by
the AFHOLD input only; 1 = hold. This is equal to taking the AFHOLD input LOW. The
bit is reset to 0, when AFHOLD input is set to LOW (i.e. at AF update or preset change).
3 RMUT Radio signal mute. 0 = no mute; 1 = mute with 1 ms ASI slope at start and stop.
SA4 SA3 SA2 SA1 SA0 HEX
(1)
MNEMONIC ADDRESSED DATA BYTE

TEF6894H/V2,518

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
IC AUDIO TONE PROCESSOR 44PQFP
Lifecycle:
New from this manufacturer.
Delivery:
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