MAX5734BUTN+ Datasheet MAX5732AUTN+, MAX5733AUTN+, MAX5732BUTN+ | P16-P18

MAX5732–MAX5735

32-Channel, 16-Bit, Voltage-Output

DACs with Serial Interface

16 ______________________________________________________________________________________

Detailed Description

The MAX5732–MAX5735 are 32-channel, 16-bit, volt-

age-output DACs (Figure 1). The devices accept a 3V

external reference input at REF. An internal offset DAC

allows all outputs to be offset (see Table 1). The devices

provide a ground-sensing function that allows the output

voltages to be referenced to a remote ground.

A 33MHz SPI-/QSPI/-MICROWIRE- and DSP-compatible

serial interface controls the MAX5732–MAX5735 (Figure 2).

Each DAC includes a double-buffered input structure to

minimize the digital noise feedthrough from the digital

inputs to the outputs, and allows for synchronous or

asynchronous updating of the outputs. The two buffers

are organized as an input register followed by a DAC

isters update the DAC registers independently or simul-

taneously with a single software or hardware command.

The MAX5732–MAX5735 also have a DOUT that allows

for read-back or daisy chaining multiple devices.

The MAX5732–MAX5735 analog and digital sections

have separate power inputs. Separate power inputs are

also provided for the output buffer amplifiers.

Proprietary deglitch circuits prevent output glitches at

power-up and eliminate the need for power sequenc-

ing. A software-shutdown mode allows efficient power

management. The MAX5732–MAX5735 consume 50µA

of supply current in shutdown.

All DACs provide buffered outputs that can drive 10kΩ

in parallel with 100pF. The MAX5732 has a 0 to +5V

output range; the MAX5733 has a 0 to +10V output

range; the MAX5734 has a -2.5V to +7.5V output range;

and the MAX5735 has a -5V to +5V output range.

External Reference Input (REF)

The REF voltage sets the full-scale output voltage for all

32 DACs. REF accepts a +3V ±3% input. Reference

voltages outside these limits can result in a degradation

of device performance.

REF is a buffered input. The typical input impedance is

10MΩ, and it does not vary with code. Use a high-

accuracy, low-noise voltage reference such as the

MAX6126AASA30 (3ppm/°C temp drift and 0.02% initial

accuracy) to improve static accuracy. REF does not

accept AC signals.

Ground Sense (GS)

The MAX5732–MAX5735 include a GS that allows the

output voltages to be referenced to a remote ground.

The GS input voltage range (V

) is -0.5V to +0.5V.

is added to the output voltage with unity gain. The

resulting output voltage must be within the valid output-

voltage range set by the power supplies. See the

Output Amplifiers (OUT0–OUT31) section for the effect

of the GS inputs on the DAC outputs.

Offset DAC

The MAX5732–MAX5735 feature an offset DAC that

determines the output voltage range. While each part

number has an output voltage range associated with it,

it is the offset DAC that determines the end-point volt-

ages of the range. Table 1 shows the offset DAC code

required during power-up.

SCLK

XX 1 2 3 32 X

DIN

D0C0C1C2

CS2

CS1

CSS

SCS

CSPWL

CSPWH

(DSP MODE)

(µC MODE)

Figure 2. Serial-interface Timing

MAX5732–MAX5735

32-Channel, 16-Bit, Voltage-Output

DACs with Serial Interface

______________________________________________________________________________________ 17

Note: The offset DAC of every device can be pro-

grammed with any of the four output voltage ranges.

However, the specifications in the Electrical

Characteristics table are only guaranteed (production

tested) for the offset code associated with each partic-

ular part number. For example, the MAX5734 specifica-

tions are only valid with the MAX5734 offset- DAC code

shown in Table 1.

The offset DAC is summed with GS (Figure 1). The offset

DAC can also cancel the offset of the output buffers.

Any change in the offset DAC affects all 32 DACs.

The offset DAC is also configured identically to the

other 32 DACs with an input and DAC register. Write to

the offset DAC through the serial interface by using

control bits C2, C1, and C0 = 001 followed by the data

bits D15–D0. The CLR command affects the offset DAC

as well as the other DACs.

The data format for the offset DAC codes are: control bits

C2, C1, and C0 = 011, address bits A5–A0 = 100000, 7

don’t-care bits, and 16 data bits as shown in Table 2.

Output Amplifiers (OUT0–OUT31)

All DAC outputs are internally buffered. The internal

buffers provide gain, improved load regulation, and tran-

sition glitch suppression for the DAC outputs. The output

buffers slew at 1V/µs and can drive 10kΩ in parallel with

100pF. The output buffers are powered by AV

and

. AV

and V

determine the maximum output

voltage range of the device.

The input code, the voltage reference, the offset DAC

output, the voltage on GS, and the gain of the output

amplifier determine the output voltage. Calculate V

OUT

as follows:

where GAIN = 5/3 for the MAX5732, or GAIN = 10/3 for

the MAX5733/MAX5734/MAX5735.

Load-DAC (LDAC) Input

The MAX5732–MAX5735 feature an active-low LDAC

logic input that allows the outputs OUT_ to update

asynchronously. Keep LDAC high during normal opera-

tion (when the device is controlled only through the ser-

ial interface). Drive LDAC low to simultaneously update

all DAC outputs with data from their respective input

registers. Figure 3 shows the LDAC timing with respect

to OUT_.

A software command can also activate the LDAC oper-

ation. To activate LDAC by software, set control bits

GAIN V DAC code offset DAC code

OUT

REF

××

()

−

PART NUMBER D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

MAX5732 0000000000000000

MAX5733 0000000000000000

MAX5734 0100000000000000

MAX5735 1000000000000000

Table 1. Offset DAC Codes

OUT_

±0.5 LSB

LDAC

Figure 3.

LDAC

Timing

Note: For the MAX5732, the maximum code for the offset DAC is 16384. For the MAX5733/MAX5734/MAX5735, the maximum code

for the offset DAC is 40000.

Table 2. Serial Data Format

CONTROL

BITS

ADDRESS

BITS

DON’T-

CARE

BITS

DATA BITS

C2, C1,

AND C0

A5–A0 — D15–D0

011 100000 XXXXXXX See table 1

MAX5732–MAX5735

32-Channel, 16-Bit, Voltage-Output

DACs with Serial Interface

18 ______________________________________________________________________________________

C2, C1, and C0 = 010, address bits A5–A0 = 111111,

and all data bits to don’t care. See Table 3 for the data

format. This operation updates all DAC outputs.

Note: The software load DAC does not affect the offset DAC.

Clear (

CLR

)

The MAX5732–MAX5735 feature an active-low CLR

logic input that sets all channels including the offset

DAC to 0V (code 0000hex). The offset DAC needs to be

reprogrammed after CLR is asserted. Driving CLR low

clears the contents of both the input and DAC registers.

The serial interface can also issue a software clear com-

mand. Setting the control bits C2, C1, and C0 = 111

(Table 4) performs the same function as driving logic-

input CLR low. Table 4 shows the clear-data format for

the software-controlled clear command. This register-

reset process cannot be interrupted. All serial input data

is ignored until the entire reset process is complete.

Serial Interface

A 3-wire SPI-/QSPI-/MICROWIRE- and DSP-compatible

serial interface controls the MAX5732–MAX5735. The

interface requires a 32-bit command word to control the

device. The command word consists of 3 control bits, 6

address bits, 7 don’t-care bits, and 16 data bits. Table 5

shows the general serial-data format. The control bits

control various write and read commands as well as the

load DAC and clear commands. Table 6 shows the con-

trol-bit functions. The address bits select the register(s)

to be written. Table 7 shows the address functions. The

data bits control the value of the DAC outputs.

Table 3. Load-DAC Data Format

CONTROL

BITS

ADDRESS

BITS

DON’T-

CARE

BITS

DATA BITS

C2, C1,

AND C0

A5–A0 — D15–D0

010 111111 XXXXXXX XXXXXXXXXXXXXXXX

Table 4. Clear-Data Format

CONTROL

BITS

ADDRESS

BITS

DON’T-

CARE

BITS

DATA BITS

C2, C1,

AND C0

A5–A0 — D15–D0

111 See table 7 XXXXXXX XXXXXXXXXXXXXXXX

Table 5. Serial-Data Format

CONTROL

BITS

ADDRESS

BITS

DON’T-

CARE

BITS

DATA BITS

MSB LSB

C2, C1,

and C0

A5–A0 XXXXXXX D15–D0

Table 6. Control-Bit Functions

CONTROL

BITS

C2 C1 C0

CONTROL-BIT DESCRIPTION

000

No operation (NOP); no internal registers

change state. The NOP command can be

passed to DOUT depending on the state of the

configuration register. Address bits A5–A0 and

data bits D15–D0 are ignored.

001

Loads D15–D0 into the input register(s) for the

selected address. Depending on the address

bits, this command could write to:

The configuration register (A[5:0] = 100001)

One of the i np ut r eg i ster s of the 32 D AC channel s

All 32 DAC input registers (A[5:0] = 111111)

The offset D AC i np ut r eg i ster ( A[ 5:0] = 100000)

010

Loads DAC register(s) from the input register(s).

Depending on the address bits, this command

can update one or all of the DAC registers from

the stored input register value(s). Data bits

D15–D0 are ignored.

011

Write-through; loads D15–D0 into the input and

DAC registers, depending on the address bits.

100

Read command; depending on the address bits,

one of the DAC-register values or the

configuration-register value may be read back

through DOUT. Data bits D15–D0 are ignored.

1 0 1 Reserved for internal testing; do not use.

1 1 0 Reserved for internal testing; do not use.

111

C l ear r eg i ster ( s) ; d ep end i ng on the ad d r ess b i ts,

one or al l r eg i ster s ( excep t the offset- D AC r eg i ster s)

ar e cl ear ed to zer o. D ata b i ts D 15–D 0 ar e i g nor ed .

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MAX5734BUTN+

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Digital to Analog Converters - DAC 10-Bit 32Ch Precision DAC

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