REVISION A 5/20/16
840011 DATA SHEET
6 FEMTOCLOCKS™ CRYSTAL-TO-LVCMOS/
LVTTL CLOCK GENERATOR
APPLICATION INFORMATION
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. The 840011 provides separate power
supplies to isolate any high switching noise from the outputs to the
internal PLL. V
DD
and V
DDA
should be individually connected to the
power supply plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance, power
supply isolation is required. Figure 1 illustrates how a 10Ω resistor
along with a 10μF and a .01μF bypass capacitor should be con-
nected to each V
DDA
pin.
POWER SUPPLY FILTERING TECHNIQUES
FIGURE 1. POWER SUPPLY FILTERING
10Ω
V
DDA
10μF
.01μF
3.3V
.01μF
V
DD
FIGURE 2. CRYSTAL INPUt INTERFACE
CRYSTAL INPUT INTERFACE
The 840011 has been characterized with 18pF parallel
resonant crystals. The capacitor values, C1 and C2, shown in
Figure 2 below were determined using a 26.5625MHz, 18pF
parallel resonant crystal and were chosen to minimize the ppm
error. The optimum C1 and C2 values can be slightly adjusted for
different board layouts.
