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LT3482IUD#TRPBF

P1-P3P4-P6P7-P9P10-P12
LT3482
4
3482fa
Oscillator Frequency vs
Temperature
Switch Current Limit
vs Duty Cycle
Switch Current Limit vs
Temperature
Current Monitor Output vs MONIN APD Current Monitor Accuracy
APD Current Monitor Accuracy
vs Temperature
TYPICAL PERFOR A CE CHARACTERISTICS
UW
TEMPERATURE (°C)
–50
900
1000
1200
25 75
3482 G01
800
700
–25 0
50 100 125
600
500
1100
FREQUENCY (kHz)
f
SET
= 2V
f
SET
= 0V
DUTY CYCLE (%)
0
SWITCH CURRENT LIMIT (mA)
150
200
250
60
100
3482 G02
100
50
0
20 40 80
300
350
400
TEMPERATURE (°C)
–50
SWITCH CURRENT LIMIT (mA)
340
25
3482 G03
280
240
–25 0 50
220
200
360
320
300
260
75 100 125
MONIN (V)
10
18
I
MON
(µA)
19
20
21
22
20 30 40 50
3482 G04
60 70 80 90
I
APD
= 100µA
I
APD
(A)
1.0E-08 1.0E-06 1.0E-04 1.0E-02
1.0E-02
1.0E-03
1.0E-04
1.0E-05
1.0E-06
1.0E-07
1.0E-08
1.0E-09
3482 G05
I
MON
(A)
MONIN = 90V
TEMPERATURE (°C)
–50
ERROR (%)
–2
0
2
25 75
3482 G06
–4
–6
–25 0
50 100 125
–8
–10
I
APD
= 2.5mA
I
APD
= 10µA
I
APD
= 250nA
MONIN = 90V
Current Monitor Voltage Drop
vs Reference Current
REFERENCE CURRENT (A)
1.00E-07 1.00E-05 1.00E-03
5
6
7
4
3
2
1
0
MONIN – APD (V)
Switch Saturation Voltage (V
CESAT
)
SWITCH CURRENT (mA)
0
V
CESAT
(mV)
200
250
300
150 250
3482 G08
150
100
50 100
200 300 350
50
0
FB Pin Voltage vs Temperature
TEMPERATURE (°C)
–50
FB PIN VOLTAGE (V)
1.24
1.25
25 75
3482 G09
1.23
–25 0
50 100 125
1.22
V
IN
= 16V
V
IN
= 3V
(T
A
= 25°C unless otherwise specifi ed)
LT3482
5
3482fa
UU
U
PI FU CTIO S
APD (Pin 2): Connect APD cathode to this pin.
MONIN (Pin 3): Current Monitor Power Supply Pin. An
external lowpass fi lter can be included here to further
reduce supply voltage ripple.
V
OUT2
(Pin 4): Voltage Doubler Output Pin. Put a 50V
rated capacitor between this pin and V
OUT1
. Tie a resistor
divider to the FB pin and GND.
V
OUT1
(Pin 5): Boost Output Pin. Put a capacitor between
this pin and the GND plane. Minimize the length of the
trace to the capacitor.
PUMP (Pin 6): Charge Pump Pin. Put a 50V rating bypass
capacitor between SW and PUMP to form a complete volt-
age doubler with the internal integrated Schottky diodes.
Minimize trace length to the capacitor.
SW (Pins 7, 8): Switch Pin. Minimize the trace length on
this pin to reduce EMI.
GND (Pins 9, 10): Ground. Pins connected internally. For
best performance, connect both pins to board ground.
V
IN
(Pin 11): Input Supply Pin. This pin must be locally
bypassed.
SHDN (Pin 12): Shutdown Pin. Tie to 1.5V or higher to
enable device; 0.4V or less to disable device. This pin also
functions as soft-start between 1.5V and 2V.
CTRL (Pin 13): Internal Reference Override Pin. This allows
the FB voltage to be externally set between 0V and 1.2V.
Tie this pin higher than 1.5V to use the internal reference
of 1.235V.
FB (Pin 14): Feedback Pin. Connect the output resistor
divider tap here.
f
SET
(Pin 15): Oscillator Frequency Selection Pin. Tie this
pin to above 1.5V or higher to select the higher switching
frequency of 1.1MHz. For lower switching frequency, tie
to GND.
MON (Pin 16): Current Monitor Output Pin. It sources a
current equal to 20% of the APD current and converts to
a reference voltage through an external resistor.
Exposed Pad (Pin 17): GND. This pin must be soldered
to the PCB.
LT3482
6
3482fa
Σ
–
+
+
–
+
R
C
EAMP
A1
A2
PWM
COMPARATOR
CURRENT
SENSE
AMPLIFIER
DRIVER
C
C
C
S
R
Q1
Q
S
–
+
RAMP
GENERATOR
APD
CURRENT
MIRROR
1.235V
REFERENCE
650kHz/1.1MHz
OSCILLATOR
CONTROL
BLOCK
11
V
IN
V
IN
10
GND
12
SHDN
R
S
V
IN
9
GND
4
V
OUT2
3
MONIN
2
APD
1
NC
3482 BD
13
CTRL
14
FB
16
MON
6
PUMP
D3
D2
D1
8
SW
C
FLY
C2
C3
R1
FB
R2
C1
L1
5
V
OUT1
R3
15
f
SET
C
PL
C4
7
SW
FU CTIO AL DIAGRA
U
U
W
OPERATIO
U
The LT3842 boost converter uses a constant frequency
current mode control scheme to provide excellent line
and load regulation. Operation can be best understood by
referring to the Functional Diagram. At the start of each
oscillator cycle, the SR latch is set, which turns on the
power switch, Q1. A voltage proportional to the switch
current is added to a stabilizing ramp and the resulting sum
is fed into the positive terminal of the PWM comparator,
A2. When this voltage exceeds the level at the negative
input of A2, the SR latch is reset turning off the power
switch. The level at the negative input of A2 is set by the
error amplifi er A1, and is simply an amplifi ed version of the
difference between the feedback voltage and the reference
voltage of 1.235V, or externally provided CTRL voltage.
In this manner, the error amplifi er sets the correct peak
current level to keep the output in regulation. If the error
amplifi er’s output increases, more current is delivered to
the output; if it decreases, less current is delivered.
The LT3482 has an integrated high side APD current moni-
tor with a 5:1 ratio. The MONIN pin can accept a supply
voltage up to 90V, which is suitable for APD photodiode
applications. The MON pin has an open-circuit protection
feature and is internally clamped to 11.5V.
If an APD is tied to the APD pin, the current will be mir-
rored to the MON pin and converted to a voltage signal
by the resistor R3. This voltage signal can be used to
drive an external control block to adjust the APD voltage
by adjusting the feedback threshold of EAMP A1 through
the CTRL input.
P1-P3P4-P6P7-P9P10-P12

LT3482IUD#TRPBF

Mfr. #:
Buy LT3482IUD#TRPBF
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators 100V Boost DC/DC Converter w/ APD Current Monitor
Lifecycle:
New from this manufacturer.
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