LTC1453IS8#PBF

4
LTC1451
LTC1452/LTC1453
sn145123 145123fas
The denotes specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C. V
CC
= 5V (LTC1451LTC1452), V
CC
= 3V (LTC1453).
LOAD CURRENT (mA)
0.0001
MINIMUM SUPPLY VOLTAGE (V)
110
5.4
5.2
5.0
4.8
4.6
4.4
4.2
4.0
1451/2/3 G01
0.010.001 0.1 100
V
OUT
< 1LSB
TEMPERATURE (°C)
–55
SUPPLY CURRENT (µA)
–25
5
35 65
1451/2/3 G03
95
450
440
430
420
410
400
390
380
370
360
350
125
V
CC
= 5.5V
V
CC
= 4.5V V
CC
= 5V
LOAD CURRENT (mA)
0.0001
MINIMUM SUPPLY VOLTAGE (V)
110
4.50
4.25
4.00
3.75
3.50
3.25
3.00
2.75
2.50
2.25
1451/2/3 G02
0.010.001 0.1 100
V
OUT
< 1LSB
LTC1451
Supply Current vs Temperature
LTC1451 Minimum Supply
Voltage vs Load Current
LTC1453 Minimum Supply
Voltage vs Load Current
Note 3: Load is 5k in parallel with 100pF.
Note 4: DAC switched between all 1s and the code corresponding to V
OS
for the part, i.e., LTC1451: code 18; LTC1453: code 30.
Note 5: Digital inputs at 0V or V
CC
.
Note 1: Absolute Maximum Ratings are those values beyond which the life
of the device may be impaired.
Note 2: Nonlinearity is defined from the first code that is greater than or
equal to the maximum offset specification to code 4095 (full scale).
LTC1451/LTC1452 LTC1453
SYMBOL PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
Digital I/O
V
IH
Digital Input High Voltage 2.4 2.0 V
V
IL
Digital Input Low Voltage 0.8 0.6 V
V
OH
Digital Output High Voltage I
OUT
= –1mA V
CC
– 1.0 V
CC
– 0.7 V
V
OL
Digital Output Low Voltage I
OUT
= 1mA 0.4 0.4 V
I
LEAK
Digital Input Leakage V
IN
= GND to V
CC
±10 ±10 µA
C
IN
Digital Input Capacitance Guaranteed by Design 10 10 pF
Not Subject to Test
Switching
t
1
D
IN
Valid to CLK Setup 40 60 ns
t
2
D
IN
Valid to CLK Hold 00 ns
t
3
CLK High Time 40 60 ns
t
4
CLK Low Time 40 60 ns
t
5
CS/LD Pulse Width 50 80 ns
t
6
LSB CLK to CS/LD 40 60 ns
t
7
CS/LD Low to CLK 20 30 ns
t
8
D
OUT
Output Delay C
LOAD
= 15pF 150 220 ns
t
9
CLK Low to CS/LD Low 20 30 ns
ELECTRICAL CHARACTERISTICS
TYPICAL PERFOR A CE CHARACTERISTICS
UW
5
LTC1451
LTC1452/LTC1453
sn145123 145123fas
LOAD RESISTANCE ()
10
OUTPUT SWING (V)
100 1k 10k
1451/2/3 G05
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
FULL SCALE
R
L
TIED TO GND
ZERO SCALE
R
L
TIED TO V
CC
V
CC
= 5V
OUTPUT SINK CURRENT (mA)
OUTPUT PULL-DOWN VOLTAGE (mV)
1000
100
10
1
0.1
0.0001 0.1 1 10 100
1451/2/3 G06
0.001 0.01
125°C
–55°C
25°C
LOGIC INPUT VOLTAGE (V)
0
SUPPLY CURRENT (mA)
1.15
1.05
0.95
0.85
0.75
0.65
0.55
0.45
0.35
4.0
1451/2/3 G04
1.0 1.5 2.5 3.5 4.50.5
2.0
3.0
5.0
ALL DIGITAL INPUTS
TIED TOGETHER
LTC1451
Supply Current vs Logic Input
Voltage
LTC1451
Output Swing vs Load Resistance
LTC1451
Pull-Down Voltage vs Output Sink
Current Capability
TEMPERATURE (°C)
–55
OFFSET VOLTAGE (µV)
–25
5
35 65
1451/2/3 G07
95
900
800
700
600
500
400
300
125
CODE
0
DNL ERROR (LSB)
0.5
0.0
0.5
1024 2048 2560
1451/2/3 TA02
512 1536 3072 3584
4095
LTC1451
Differential Nonlinearity (DNL)
CODE
0
ERROR (LSB)
2.0
1.6
1.2
0.8
0.4
0
0.4
0.8
1.2
1.6
2.0
1024
2048
2560
1451/2/3 G09
512 1536
3072
3584
4095
V
CC
= 5V
INTERNAL REFERENCE
T
A
= 25°C
LTC1451
Integral Nonlinearity (INL)
0.2LSB/DIV
LTC1452
Total Harmonic Distortion + Noise
vs Frequency
LTC1451
Broadband Output Noise
FREQUENCY (Hz)
TOTAL HARMONIC DISTORTION + NOISE (dB)
–40
–50
–60
–70
–80
–90
100
10050 10k 100k
1451/2/3 G08
1k
V
CC
= 5V
V
IN
= 2V
P-P
V
OUT
= 4V
P-P
LTC1451
Offset Voltage vs Temperature
5ms/DIV
CODE = FFFH
BW = 3Hz TO 1.4MHz
GAIN = 1000
1451/2/3 G10
TYPICAL PERFOR A CE CHARACTERISTICS
UW
6
LTC1451
LTC1452/LTC1453
sn145123 145123fas
GND: Ground.
REF: The Output of the Internal Reference and the Input
to the DAC Resistor Ladder. An external reference with
voltage up to V
CC
/2 may be used for the LTC1452.
V
OUT
: The Buffered DAC Output.
V
CC
: The Positive Supply Input. 4.5V V
CC
5.5V
(LTC1451), 2.7 V
CC
5.5V (LTC1452/LTC1453). Re-
quires a bypass capacitor to ground.
CLK: The TTL Level Input for the Serial Interface Clock.
D
IN
: The TTL Level Input for the Serial Interface Data. Data
on the D
IN
pin is latched into the shift register on the rising
edge of the serial clock.
CS/LD: The TTL Level Input for the Serial Interface Enable
and Load Control. When CS/LD is low the CLK signal is
enabled, so the data can be clocked in. When CS/LD is
pulled high, data is loaded from the shift register into the
DAC register, updating the DAC output.
D
OUT
: The Output of the Shift Register which Becomes
Valid on the Rising Edge of the Serial Clock.
B11
MSB
B10
t
1
t
9
B1
t
6
B0
LSB
B11
CURRENT WORD
t
7
t
2
t
4
t
3
t
8
CLK
D
IN
D
OUT
CS/LD
t
5
1451/2/3 TD
B0
PREVIOUS WORD
B11
PREVIOUS WORD
B10
B1
B0
DAC
REGISTER
LD
+
REFERENCE
LTC1451: 2.048V
LTC1453: 1.22V
12-BIT
SHIFT
REGISTER
POWER-ON
RESET
11451/2/3 BD
CLK
1
D
IN
2
D
OUT
4
V
OUT
7
REF
6
GND
5
V
CC
8
3
CS/LD
12-BIT DAC
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LTC1453IS8#PBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Digital to Analog Converters - DAC 12-Bit Vout DAC w/Vref, Serial I/O
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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