PS11016

MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>
PS11016
FLAT-BASE TYPE
INSULATED TYPE
Jan. 2000
Supply voltage ripple
Input on voltage
Input off voltage
PWM Input frequency
Arm shoot-through blocking time
Supply voltage
V
DH
, V
DB
VCIN(on)
VCIN(off)
fPWM
tdead
10.0
16.50
18.00
11.55
t
d(read)
ICL(H)
ICL(L)
±IOL
SC
OT
OTr
UV
DH
UVDHr
OVDH
OVDHr
UVDB
UVDBr
tdV
IFO(H)
IFO(L)
0.77
t
xx
ELECTRICAL CHARACTERISTICS (Tj = 25°C, VDH = 15V, VDB = 15V unless otherwise noted)
3.37
Idle
Active
Trip level
Reset level
Trip level
Reset level
Trip level
Reset level
Trip level
Reset level
Filter time
Idle
Active
Ic = 0A
Ic = I
OP(200%)
Ic = –I
OP(200%)
t
int
VCO
V
C+
(200%)
V
C–
(200%)
|VCO|
V
C+
VC–
VC(200%)
T
C = –20 ~ +100°C,
Tj 125°C
V
DH = 15V
T
C = –20°C ~ 100°C
(Fig. 4)
T
C 100°C, Tj 125°C
V
DH = 15V, TC = –20°C ~ +100°C (Note 3)
PWM input frequency
Condition
Symbol
Ratings
f
PWM
Min. Typ. Max.
Unit
VDH = 15V, TC = –20°C ~ 100°C
Ic > I
OP(200%), VDH = 15V
(Fig. 4)
|V
CO-VC±(200%)|
After input signal trigger point (Fig. 8)
Fault output current
Open collector output
V
D = 15V, TC = –20°C ~ 100°C (Note 4)
Tj = 25°C (Fig. 7) (Note 5)
Analogue signal over all linear variation
Item
tdead
Allowable input on-pulse width
Allowable input signal dead time for
blocking arm shoot-through
Relates to corresponding input (Except break part)
Analogue signal linearity with output current
Offset change area vs temperature
Analogue signal output voltage limit
r
CH
Analogue signal data hold accuracy
Analogue signal reading time
Correspond to max. 500µs data hold period
only, Ic = I
OP(200%) (Fig. 5)
CL warning operation level
Short circuit over current trip level
1
2.5
1.87
4.0
–5
31.2
50.6
100
11.05
Open collector output
65
2.27
1.17
15
1.1
1
38.0
65.0
110
90
11.0
12.00
12.50
19.20
10
1
15
500
100
2.57
1.47
3.67
0.7
1
5
46.0
120
12.0
12.5
12.75
13.25
20.15
18.65
1
—3
——
kHz
µs
µs
ns
V
V
V
mV
V
V
V
%
µs
µA
mA
A
A
°C
°C
V
V
V
V
µs
µA
mA
17.50
Relates to corresponding inputs,
(Except brake part), T
C = –20°C ~ +100°C
Input inter-lock sensing
2.97
Signal output current of
CL operation
Over temperature
protection
Supply circuit under &
over voltage protection
11.510.5
V
V
V
DH = 15V
(Note 3) : (a) Allowable minimum input on-pulse width : This item applies to P-side circuit only.
(b) Allowable maximum input on-pulse width : This item applies to both P-side and N-side circuits excluding the brake circuit.
(Note4) : CL output : The "current limit warning (CL) operation circuit outputs warning signal whenever the arm current exceeds this limit. The
circuit is reset automatically by the next input signal and thus, it operates on a pulse-by-pulse scheme.
(Note5) : The short circuit protection works instantaneously when a high short circuit current flows through an internal IGBT rising up momen-
tarily. The protection function is, thus meant primarily to protect the ASIPM against short circuit distraction. Therefore, this function is
not recommended to be used for any system load current regulation or any over load control as this might, cause a failure due to
excessive temperature rise. Instead, the analogue current output feature or the over load warning feature (CL) should be appropri-
ately used for such current regulation or over load control operation. In other words, the PWM signals to the ASIPM should be shut
down, in principle, and not to be restarted before the junction temperature would recover to normal, as soon as a fault is feed back
from its F
O1 pin of the ASIPM indicating a short circuit situation.
RECOMMENDED CONDITIONS
V
400 (max.)
Applied across P-N terminals
Condition
Symbol
Item Ratings
VCC
Unit
VDH, VDB
Control Supply voltage
Applied between V
DH-GND, CBU+-CBU–, CBV+-CBV–,
C
BW+-CBW–
Using application circuit
Using application circuit
15±1.5
±1 (max.)
0 ~ 0.3
4.8 ~ 5.0
2 ~ 15
2.5 (min.)
V
V/µs
V
V
kHz
µs
MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>
PS11016
FLAT-BASE TYPE
INSULATED TYPE
Jan. 2000
200–200
Analogue output signal
data hold range
1
2
3
4
5
4003001000–100–300–400
0
V
C
+(200%)
V
C0
V
C
(200%)
VC(V)
VC+
V
C
min
max
Real load current peak value.(%)(Ic=Io2)
V
DH
=15V
T
C
=
20
~
100˚C
(Fig. 4)
Note : Input interlock protection circuit ; It is operated when the input signals for any upper-arm / lower-arm pair of a phase are simulta-
neously in “LOW” level.
By this interlocking, both upper and lower IGBTs of this mal-triggered phase are cut off, and “F
O” signal is outputted. After an “input
interlock” operation the circuit is latched. The “F
O
” is reset by the high-to-low going edge of either an upper-leg, or a lower-leg input,
whichever comes in later.
V
CH
(5
µ
s) V
CH
(505
µ
s)
0V
V
C
500µs
r
CH
=
V
CH
(505
µ
s)-V
CH
(5
µ
s)
V
CH
(5
µ
s)
Note ; Ringing happens around the point where the signal output
voltage changes state from “analogue” to “data hold” due
to test circuit arrangement and instrumentational trouble.
Therefore, the rate of change is measured at a 5 µs delayed point.
0V
0V
0V
0V
0V
Input signal V
CIN(p) of each phase upper arm
Input signal V
CIN(n) of each phase lower arm
Gate signal V
o(p) of each phase upper arm
(ASIPM internal)
Gate signal V
o(n) of each phase upper arm
(ASIPM internal)
Error output F
O1
Note : Short circuit protection operation. The protection operates with “FO” flag and reset on a pulse-by-pulse scheme. The protection by
gate shutdown is given only to the IGBT that senses an overload (excluding the IGBT for the “Brake”).
S
C
delay time
Short circuit sensing signal V
S
Error output F
O1
Gate signal Vo of each phase
upper arm(ASIPM internal)
Input signal V
CIN
of each phase
upper arm
0V
0V
0V
0V
Fig. 4 OUTPUT CURRENT ANALOGUE SIGNALING
LINEARITY
Fig. 5 OUTPUT CURRENT ANALOGUE SIGNALING
“DATA HOLD” DEFINITION
Fig. 6 INPUT INTERLOCK OPERATION TIMING CHART
Fig. 7 TIMING CHART AND SHORT CIRCUIT PROTECTION OPERATION
MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module>
PS11016
FLAT-BASE TYPE
INSULATED TYPE
Jan. 2000
R
U
P
,V
P
,W
P
,U
N
,V
N
,W
N
,Br
F
01
,F
02
,F
03
,CL
CU,CV,CW
GND(Logic)
ASIPM
5V
CPU
R
5.1k
10k
0.1nF0.1nF
on
on
on
on
0
0
0
V
PN
DC-Bus voltage
Control voltage supply
Boot-strap voltage
N-Side input signal
P-Side input signal
Brake input signal
F
O
1 output signal
V
DB
V
CIN(N)
V
CIN(P)
V
CIN(Br)
F
OI
V
DH
b)
a)
PWM starts
N-side IGBT Current N-side FWDi Current
t(hold)
td(read)
Delay time
+I
CL
–I
CL
on
off
on
off
0
0
on
off
0
Ref
V
CIN
V(hold)
I
C
(V
S
)
V
C
V
CL
Fig. 8 INVERTER OUTPUT ANALOGUE CURRENT SENSING AND SIGNALING TIMING CHART
Fig. 10 RECOMMENDED I/O INTERFACE CIRCUIT
Fig. 9 START-UP SEQUENCE
Normally at start-up, Fo and CL output signals will be pulled-up
High to Supply voltage (OFF level); however, F
O1 output may fall to
Low (ON) level at the instant of the first ON input pulse to an N-Side
IGBT. This can happen particularly when the boot-strap capacitor is
of large size. F
O1 resetting sequence (together with the boot-strap
charging sequence) is explained in the following graph
a) Boot-strap charging scheme :
Apply a train of short ON pulses at all N-IGBT input pins for ad-
equate charging (pulse width = approx. 20µs number of pulses =10
~ 500 depending on the boot-strap capacitor size)
b) F
O1 resetting sequence:
Apply ON signals to the following input pins : Br Un/Vn/Wn
Up/Vp/Wp in that order.

PS11016

Mfr. #:
Manufacturer:
Description:
MOD IPM 3PHASE IGBT 600V 30A
Lifecycle:
New from this manufacturer.
Delivery:
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