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8P34S1102NLGI

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18
IDT8P34S1102NLGI REVISION A FEBRUARY 26, 2014 1 ©2014 Integrated Device Technology, Inc.
DATA SHEET
1:2 LVDS Output 1.8V Fanout Buffer IDT8P34S1102I
General Description
The IDT8P34S1102I is a high-performance differential LVDS fanout
buffer. The device is designed for the fanout of high-frequency, very
low additive phase-noise clock and data signals. The
IDT8P34S1102I is characterized to operate from a 1.8V power
supply. Guaranteed output-to-output and part-to-part skew
characteristics make the IDT8P34S1102I ideal for those clock
distribution applications demanding well-defined performance and
repeatability. One differential input and two low skew outputs are
available. The integrated bias voltage reference enables easy
interfacing of single-ended signals to the differential device input. The
device is optimized for low power consumption and low additive
phase noise.
Features
• Two low skew, low additive jitter LVDS output pairs
• One differential clock input pair
• Differential CLK, nCLK pairs can accept the following differential
input levels: LVDS, CML
• Maximum input clock frequency: 1.2GHz
• Output skew: 3ps (typical)
• Propagation delay: 400ps (maximum)
• Low additive phase jitter, RMS; f
REF
= 156.25MHz,
12kHz- 20MHz: 42fs (typical)
• Maximum device current consumption (I
EE
): 48mA
• Full 1.8V supply voltage
• Lead-free (RoHS 6), 16-Lead VFQFN packaging
• -40°C to 85°C ambient operating temperature
Block Diagram Pin Assignment
IDT8P34S1102I
16-lead VFQFN
3mm x 3mm x 0.925mm package body
1.7mm x 1.7mm ePad Size
NL Package
Top View
V
REF
V
DD
CLK
nCLK
V
REF
Q0
nQ0
Q1
nQ1
nQ1
Q1
nQ0
Q0
12 11 10 9
nc
13 8
V
REF
nc
14 7
nCLK
nc
15 6
CLK
GND
16 5
VDD
1234
GND
nc
nc
nc
IDT8P34S1102I Data Sheet 1:2 LVDS Output 1.8V Fanout Buffer
IDT8P34S1102NLGI REVISION A FEBRUARY 26, 2014 2 ©2014 Integrated Device Technology, Inc.
Pin Description and Pin Characteristic Tables
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of the product at these conditions or any conditions beyond those listed in the DC Characteristics or
AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Table 1. Pin Descriptions
Note 1.
1. Pulldown and Pullup refers to an internal input resistors. See Table 2, Pin Characteristics, for typical values.
Number Name Type Description
1, 16 GND Power
Power supply ground.
2, 3, 4, 13, 14, 15 nc Unused
Do not connect.
5V
DD
Power
Power supply pins.
6 CLK Input Pulldown
Non-inverting differential clock/data input.
7 nCLK Input
Pulldown/
Pullup
Inverting differential clock input.
8V
REF
Output
Bias voltage reference. Provides an input bias voltage for the CLK, nCLK input
pair in AC-coupled applications. Refer to Figures 2B and 2C for applicable
AC-coupled input interfaces.
9, 10 Q0, nQ0 Output
Differential output pair 0. LVDS interface levels.
11, 12 Q1, nQ1 Output
Differential output pair 1. LVDS interface levels.
Table 2. Pin Characteristics
Symbol Parameter Test Conditions Minimum Typical Maximum Units
C
IN
Input Capacitance 2 pF
R
PULLDOWN
Input Pulldown Resistor 51 k
R
PULLUP
Input Pullup Resistor 51 k
Item Rating
Supply Voltage, V
DD
4.6V
Inputs, V
I
-0.5V to V
DD
+ 0.5V
Outputs, I
O
Continuous Current
Surge Current
10mA
15mA
Input Sink/Source, I
REF
±2mA
Maximum Junction Temperature, T
J,MAX
125°C
Storage Temperature, T
STG
-65°C to 150°C
ESD - Human Body Model
Note 1.
1. According to JEDEC JS-001-2012/JESD22-C101E.
2000V
ESD - Charged Device Model
Note 1.
1500V
IDT8P34S1102I Data Sheet 1:2 LVDS Output 1.8V Fanout Buffer
IDT8P34S1102NLGI REVISION A FEBRUARY 26, 2014 3 ©2014 Integrated Device Technology, Inc.
DC Electrical Characteristics
Table 3A. Power Supply DC Characteristics, V
DD
= 1.8V ± 5%, T
A
= -40°C to 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
DD
Power Supply Voltage 1.71 1.8 1.89 V
I
DD
Power Supply Current Q0 to Q1 terminated 100 between nQx, Qx 40 48 mA
Table 3B. Differential Input Characteristics, V
DD
= 1.8V ± 5%, T
A
= -40°C to 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
I
IH
Input High Current CLK, nCLK V
IN
= V
DD
= 1.89V 150 µA
I
IL
Input Low Current
CLK V
IN
= 0V, V
DD
= 1.89V -10 µA
nCLK V
IN
= 0V, V
DD
= 1.89V -150 µA
V
REF
Reference Voltage for Input
Bias
Note 1.
1. V
REF
specification is applicable to the AC-coupled input interfaces shown in Figures 2B and 2C.
I
REF
= +100µA, V
DD
= 1.8V 0.9 1.30 V
V
PP
Peak-to-Peak Voltage V
DD
= 1.89V 0.2 1.0 V
V
CMR
Common Mode Input Voltage
Note 2.
Note 3.
2. Common mode input voltage is defined as crosspoint voltage.
3. V
IL
should not be less than -0.3V and V
IH
should not be higher than V
DD
.
0.9 V
DD
– (V
PP
/2) V
Table 3C. LVDS DC Characteristics, V
DD
= 1.8V ± 5%, T
A
= -40°C to 85°C
Note 1.
1. Output drive current must be sufficient to drive up to 30cm of PCB trace (assume nominal 50 impedance)
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
OD
Differential Output Voltage outputs loaded with 100 247 454 mV
V
OD
V
OD
Magnitude Change 50 mV
V
OS
Offset Voltage 1.0 1.40 V
V
OS
V
OS
Magnitude Change 50 mV
Note3.
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8P34S1102NLGI

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Manufacturer:
IDT
Description:
Clock Drivers & Distribution 1:2 LVDS Output 1.8V Fanout Buffer
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