STA1102R Functional description
Doc ID 16470 Rev 5 7/18
3 Functional description
3.1 Equalizer
The adjustable input equalizer reduces system jitter and attenuation from long or lossy
cables. Shaping is performed by the gain stage of the equalizer to compensate the signal.
Note: 9 dB EQ is useful for signal recovery over long PCB track, e.g. 10” FR4.
3.2 Pre-emphasis
The STA1102R provides at each output a differential pair of 1-bit programmable pre-
emphasis to compensate for losses across long PCB tracks and interconnects after the re-
driver output. Below, the truth table of the pre-emphasis control is shown:
Table 3. Input equalizer truth table
EN E1 E2 Function
0xx
Low power mode:
input stage disabled for minimum power consumption
100
Normal operation mode:
both CH1 and CH2 7dB EQ
101
Normal operation mode:
CH1 7dB EQ; CH2 9dB EQ
110
Normal operation mode:
CH1 9dB EQ; CH2 7dB EQ
111
Normal operation mode:
both CH1 and CH2 9dB EQ
Table 4. Pre-emphasis truth table
EN D1 D2 Functions
0xx
Low power mode:
output driver disabled; output driven to HiZ
100
Normal operation mode:
both CH1 and CH2 0 dB pre-emphasis
101
Normal operation mode:
CH1 0 dB pre-emphasis; CH2 2.5 dB pre-emphasis
110
Normal operation mode:
CH1 2.5 dB pre-emphasis; CH2 0 dB pre-emphasis
111
Normal operation mode:
both CH1 and CH2 2.5 dB pre-emphasis
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Functional description STA1102R
8/18 Doc ID 16470 Rev 5
3.3 Input termination
The STA1102R integrates precise 50 Ω ± 10% termination resistors, pulled up to V
Cm
, on all
its differential input channels. External terminations are not required. This gives improved
performance and also minimizes the PCB board space. These on-chip termination resistors
should match the differential characteristic impedance of the transmission line.
3.4 Low power modes
There are 2 types of low power modes in the STA1102R: hardware low and auto low power
modes.
3.4.1 Hardware low power mode
The EN input activates a hardware low power mode. There is an internal pull-up resistor to
maintain the EN in the default (HIGH) state. When this low power mode is activated
(EN = L), all input and output buffers and internal bias circuitry are powered off and disabled.
Outputs are driven to HiZ in low power mode. There is a delay associated with entering
(max. 2
µs) and exiting (max. 20 µs) this hardware low power mode.
3.4.2 Auto low power mode
The auto low power mode is activated when differential voltage at either or both of the
channels is < 50 mV for more than 3
µs. During this low power mode, output of the
associated channel is driven to V
cm
and the selective circuit block is disabled to lower power
consumption. The delay associated with exiting the auto low power mode is 50 ns max.
3.5 Squelch detector
A squelch detector is integrated on the input of each of the 2 data paths. The squelch
detector is a high-speed amplitude comparator that is turned on when EN = H. The
differential input signal is monitored by the detector. When the differential input is detected
to be less than or equal to 50 mV, the input signal is considered an invalid signal and is not
passed to the output. When this happens, the corresponding output is biased to V
CM
. When
the differential input is greater than or equal to 150 mV, the input signal is considered valid
signal and is passed to the output.
The integration of the squelch detector helps the system to prevent responding to noises.
As such, it enables the device to fully support OOB signaling.
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STA1102R Application diagram
Doc ID 16470 Rev 5 9/18
4 Application diagram
Figure 3. Typical application diagram
Note: Typical circuit above is shown with CHI1 Pre-Emp of 0 dB, EQ of 7 dB; CH2 Pre-Emp
of 2.5 dB, EQ of 7 dB.
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STA1102RUTR

Mfr. #:
Manufacturer:
STMicroelectronics
Description:
Buffers & Line Drivers 3 Gbps Serial Data Redriver 100 Ohm
Lifecycle:
New from this manufacturer.
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