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AD9726BSVZRL

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25
AD9726
Rev. B | Page 6 of 24
Parameter Min Typ Max Unit
SERIAL PORT INTERFACE
SCLK Frequency (f
SCLK
) 15 MHz
SCLK Rise/Fall Time 1 ms
SCLK Pulse Width High (t
CPWH
) 30 ns
SCLK Pulse Width Low (t
CPWL
) 30 ns
SCLK Setup Time (t
CSU
) 30 ns
SDIO Setup Time (t
DSU
) 30 ns
SDIO Hold Time (t
DH
) 0 ns
SDIO/SDO Valid Time (t
DV
) 30 ns
RESET PULSE WIDTH 1.5 ns
TIMING DIAGRAMS
DAC CLOCK
DATACLOCK OUTPU
T
DATACLOCK INPUT
DATA BUS
t
DCPD-DDR
t
DSU-DDR
t
DH-DDR
04540-002
Figure 2. DDR Timing Diagram
DAC CLOCK
DATACLOCK OUTPU
T
DATACLOCK INPUT
DATA BUS
t
DCPD-SDR
t
DSU-SDR
t
DH-SDR
04540-003
Figure 3. SDR Timing Diagram
04540-100
DB0 TO DB15
CLK+/CLK–
IOUTA OR IOUTB
t
PD-BYPASS
t
DSU-BYPASS
t
DH-BYPASS
Figure 4. Data Synchronization Bypass Timing Diagram
AD9726
Rev. B | Page 7 of 24
0
4540-101
CLK+/CLK–
IOUTA OR IOUTB
t
PIPE-BYPASS
+
t
PD-BYPASS
DB0 TO DB15
Figure 5. Data Synchronization Bypass Pipeline Delay
CSB
SCLK
S
DIO (SD0)
t
CPWH
t
DSU
t
DH
t
CPWL
04540-004
SCLK SET-UP TIME
SDIO SET-UP TIME SDIO HOLD TIME SDIO (SD0) VALID TIME
SCLK PULSE WIDTH HIGH/LOW TIME
t
CSU
t
DV
Figure 6. SPI Timing Diagram
AD9726
Rev. B | Page 8 of 24
ABSOLUTE MAXIMUM RATINGS
Table 5.
THERMAL RESISTANCE
Parameter With Respect to Rating
DBVDD, AVDD1,
AVDD2
DBGND, AGND1,
AGND2
−0.3 V to 3.6 V
DVDD, CLKVDD,
ACVDD, ADVDD
DGND, CLKGND,
ACGND, ADGND
−0.3 V to 2.8 V
DBGND, AGND1,
AGND2
DBGND, AGND1,
AGND2
−0.3 V to +0.3 V
DGND, CLKGND,
ACGND, ADGND
DGND, CLKGND,
ACGND, ADGND
−0.3 V to +0.3 V
REFIO, FSDAJ AGND1
−0.3 V to AVDD1
+ 0.3 V
IOUTA, IOUTB AGND1
−1.0 V to AVDD1
+ 0.3 V
CLK± CLKGND
−0.3 V to CLKVDD
+ 0.3 V
DB[15:0]±,
DCLK_IN±,
DCLK_OUT±
DBGND
−0.3 V to DBVDD
+ 0.3 V
CSB, SCLK, SDIO,
SDO, RESET, REXT
DBGND
−0.3 V to DBVDD
+ 0.3 V
SDR_EN, SPI_DIS ADGND
−0.3 V to ADVDD
+ 0.3 V
Thermal impedance can be lowered to 23°C/W by soldering the
exposed package pad to an external heat sink (for example, the
internal PCB copper ground plane). However, this is not necessary
for the power dissipation and operating temperature range of
the AD9726.
Table 6. Thermal Resistance
Package Type θ
JA
Unit
80-Lead TQFP_EP Package, Thermally Enhanced 32 °C/W
ESD CAUTION
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25

AD9726BSVZRL

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Digital to Analog Converters - DAC 16-Bit 400 MSPS
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