Figure 1. Load Circuits for Data-Access Time Test
_______________Detailed Description
Converter Operation
The MX7575 and MX7576 use the successive-approxi-
mation technique to convert an unknown analog input
voltage to an 8-bit digital output code (see
Functional
Diagrams
). The MX7575 samples the input voltage on
an internal capacitor once (at the beginning of the con-
version), while the MX7576 samples the input signal
eight times during the conversion (see
MX7575
Track/Hold
and
MX7576 Analog Input
sections). The
internal DAC is initially set to half scale, and the com-
parator determines whether the input signal is larger
than or smaller than half scale. If it is larger than half
scale, the DAC MSB is kept. But if it is smaller, the MSB
is dropped. At the end of each comparison phase, the
SAR (successive-approximation register) stores the
results of the previous decision and determines the
next trial bit. This information is then loaded into the
DAC after each decision. As the conversion proceeds,
the analog input is approximated more closely by com-
paring it to the combination of the previous DAC bits
and a new DAC trial bit. After eight comparison cycles,
the eight bits stored in the SAR are latched into the out-
put latches. At the end of the conversion, the BUSY sig-
nal goes high, and the data in the output latches is
ready for microprocessor (µP) access. Furthermore, the
DAC is reset to half scale in preparation for the next
conversion.
Microprocessor Interface
The CS and RD logic inputs are used to initiate conver-
sions and to access data from the devices. The MX7575
and MX7576 have two common interface modes: slow-
memory interface mode and ROM interface mode. In
addition, the MX7576 has an asynchronous conversion
mode (MODE pin = low) where continuous conversions
are performed. In the slow-memory interface mode, CS
and RD are taken low to start a conversion and they
remain low until the conversion ends, at which time the
conversion result is latched. This mode is designed for
µPs that can be forced into a wait state. In the ROM
interface mode, however, the µP is not forced into a wait
state. A conversion is started by taking CS and RD low,
and data from the previous conversion is read. At the
end of the most recent conversion, the µP executes a
read instruction and starts another conversion.
For the MX7575, TP should be hard-wired to V
DD
to
ensure proper operation of the device. Spurious signals
may occur on TP, or excessive currents may be drawn
from V
DD
if TP is left open or tied to a voltage other than
V
DD
.
Slow-Memory Mode
Figure 3 shows the timing diagram for slow-memory
interface mode. This is used with µPs that have a wait-
state capability of at least 10µs (such as the 8085A),
where a read instruction is extended to accommodate
slow-memory devices. A conversion is started by exe-
cuting a memory read to the device (taking CS and RD
low). The BUSY signal (which is connected to the µP
READY input) then goes low and forces the µP into a
wait state. The MX7575 track/hold, which had been
tracking the analog input signal, holds the signal on the
third falling clock edge after RD goes low (Figure 12).
The MX7576, however, samples the analog input eight
times during a conversion (once before each compara-
tor decision). At the end of the conversion, BUSY
returns high, the output latches and buffers are updat-
ed with the new conversion result, and the µP com-
pletes the memory read by acquiring this new data.
The fast conversion time of the MX7575/MX7576
ensures that the µP is not forced into a wait state for an
excessive amount of time. Faster versions of many µPs,
MX7575/MX7576
CMOS, µP-Compatible, 5µs/10µs, 8-Bit ADCs
_______________________________________________________________________________________ 5
D_ D_
100pF
DGND DGND
+5V
100pF3k
3k
a) HIGH-Z TO V
OH
NOTE: D_ REPRESENTS ANY OF THE DATA OUTPUTS
b) HIGH-Z TO V
OL
D_ D_
10pF
DGND DGND
+5V
10pF3k
3k
a) V
OH
TO HIGH-Z b) V
OL
TO HIGH-Z
NOTE: D_ REPRESENTS ANY OF THE DATA OUTPUTS
Figure 2. Load Circuits for Data-Hold Time Test
