MX7575/MX7576
MX7575 Track/Hold
The track/hold consists of a sampling capacitor and a
switch to capture the input signal. The simplified dia-
gram of this block is shown in Figure 11. At the begin-
ning of the conversion, switch S1 is closed, and the
input signal is tracked. The input signal is held (switch
S1 opens) on the third falling edge of clock after CS
and RD go low (Figure 12). This allows a minimum of
two clock cycles for the input capacitor to be charged
to the input voltage through the switch resistance. The
time required for the hold capacitor to settle to ±1/4LSB
is typically 7ns. Therefore, the input signal is allowed
ample time to settle before it is acquired by the
track/hold. When a conversion ends, switch S1 closes,
and the input signal is tracked.
The track/hold is capable of acquiring signals with slew
rates of up to 386mV/µs (or equivalently a 50kHz sine
wave with 2.46Vp-p amplitude). Figure 13 shows the
signal-to-noise ratio (SNR) versus input frequency for
the ADC. The SNR plot is generated at a sampling rate
of 200kHz using sinusoidal inputs with a peak-to-peak
amplitude of 2.46V. The reconstructed sine wave is
passed through a 50kHz 8th-order Chebychev filter.
The improvement in SNR at high frequencies is due to
the filter cutoff.
The switching nature of the analog input results in tran-
sient currents that charge the input capacitance of the
track/hold. Keep the driving source impedance low
(below 2kΩ), so that the settling characteristics of the
track/hold are not degraded. A low driving impedance
also minimizes undesirable noise pickup and reduces
DC errors caused by transient currents at the analog
input. As with any ADC, it is important to keep external
sources of noise to a minimum during a conversion.
Therefore, keep the data bus as quiet as possible dur-
ing a conversion, especially when the track/hold is
making the transition to the hold mode.
For conversion times that are significantly longer than
5µs, the device’s accuracy may degrade slightly, as
shown in Figure 14. This degradation is due to the
charge that is lost from the hold capacitor in the pres-
ence of small on-chip leakage currents.
MX7576 Analog Input
The MX7576 analog input can also be modeled with the
switch and capacitor as shown in Figure 11. However,
unlike the MX7575, the MX7576 samples the input volt-
age eight times during a conversion (once before each
comparator decision). Therefore, the precautions that
apply to the MX7575 also apply to the MX7576. These
include minimizing the analog source impedance and
reducing noise coupling from the digital circuitry during
a conversion, especially near a sampling instant.
Reference Input
The high speed of this ADC can be partially attributed to
the “inverted voltage output” topology of the DAC that it
uses. This topology provides low offset and gain errors
and fast settling times. The input current to the DAC,
however, is not constant. During a conversion, as differ-
ent DAC codes are tried, the DC impedance of the DAC
can vary between 6kΩ and 18kΩ. Furthermore, when
the DAC codes change, small amounts of transient cur-
rent are drawn from the reference input. These charac-
teristics require a low DC and AC driving impedance for
the reference circuitry to minimize conversion errors.
Figure 15 shows the reference circuitry recommended
to drive the reference input of the MX7575/MX7576.
CMOS, µP-Compatible, 5µs/10µs, 8-Bit ADCs
8 _______________________________________________________________________________________
V
IN
C
S
0.5pF
C
H
2pF
R
ON
500Ω
S1
Figure 11. Equivalent Input Circuit
CS
RD
BUSY
INTERNAL
CLOCK
CS
RD
BUSY
EXTERNAL
CLOCK
INPUT SIGNAL HELD HERE
a) WITH EXTERNAL CLOCK
b) WITH INTERNAL CLOCK
INPUT SIGNAL HELD HERE
Figure 12. MX7575 Track/Hold (Slow-Memory Interface)
Timing Diagrams
