Philips Semiconductors Product specification
N-channel TrenchMOS transistor PHP21N06LT, PHB21N06LT
Logic level FET PHD21N06LT
AVALANCHE ENERGY LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
E
AS
Non-repetitive avalanche Unclamped inductive load, I
AS
= 9.7 A; - 34 mJ
energy t
p
= 100 µs; T
j
prior to avalanche = 25˚C;
V
DD
≤ 25 V; R
GS
= 50 Ω; V
GS
= 5 V; refer to
fig:15
I
AS
Peak non-repetitive - 19 A
avalanche current
THERMAL RESISTANCES
SYMBOL PARAMETER CONDITIONS TYP. MAX. UNIT
R
th j-mb
Thermal resistance junction - 2.7 K/W
to mounting base
R
th j-a
Thermal resistance junction SOT78 package, in free air 60 - K/W
to ambient SOT428 and SOT404 package, pcb 50 - K/W
mounted, minimum footprint
ELECTRICAL CHARACTERISTICS
T
j
= 25˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
V
(BR)DSS
Drain-source breakdown V
GS
= 0 V; I
D
= 0.25 mA; 55 - - V
voltage T
j
= -55˚C 50 - - V
V
GS(TO)
Gate threshold voltage V
DS
= V
GS
; I
D
= 1 mA 1.0 1.5 2.0 V
T
j
= 175˚C 0.5 - - V
T
j
= -55˚C - - 2.3 V
R
DS(ON)
Drain-source on-state V
GS
= 10 V; I
D
= 10 A - 55 70 mΩ
resistance V
GS
= 5 V; I
D
= 10 A - 60 75 mΩ
T
j
= 175˚C - - 158 mΩ
g
fs
Forward transconductance V
DS
= 25 V; I
D
= 10 A 5 13 - S
I
GSS
Gate source leakage current V
GS
= ±5 V; V
DS
= 0 V - 10 100 nA
I
DSS
Zero gate voltage drain V
DS
= 55 V; V
GS
= 0 V; - 0.05 10 µA
current T
j
= 175˚C - - 500 µA
Q
g(tot)
Total gate charge I
D
= 20 A; V
DD
= 44 V; V
GS
= 5 V - 9.4 - nC
Q
gs
Gate-source charge - 2.2 - nC
Q
gd
Gate-drain (Miller) charge - 5.4 - nC
t
d on
Turn-on delay time V
DD
= 30 V; R
D
= 1.2 Ω;-715ns
t
r
Turn-on rise time R
G
= 10 Ω; V
GS
= 5 V - 88 120 ns
t
d off
Turn-off delay time Resistive load - 25 40 ns
t
f
Turn-off fall time - 25 45 ns
L
d
Internal drain inductance Measured from tab to centre of die - 3.5 - nH
L
d
Internal drain inductance Measured from drain lead to centre of die - 4.5 - nH
(SOT78 package only)
L
s
Internal source inductance Measured from source lead to source - 7.5 - nH
bond pad
C
iss
Input capacitance V
GS
= 0 V; V
DS
= 25 V; f = 1 MHz - 466 650 pF
C
oss
Output capacitance - 95 135 pF
C
rss
Feedback capacitance - 71 85 pF
August 1999 2 Rev 1.500
