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PHD21N06LT,118

P1-P3P4-P6P7-P9P10-P12
Philips Semiconductors Product specification
N-channel TrenchMOS transistor PHP21N06LT, PHB21N06LT
Logic level FET PHD21N06LT
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
T
j
= 25˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
I
S
Continuous source current - - 19 A
(body diode)
I
SM
Pulsed source current (body - - 76 A
diode)
V
SD
Diode forward voltage I
F
= 20 A; V
GS
= 0 V - 1.2 1.5 V
t
rr
Reverse recovery time I
F
= 20 A; -dI
F
/dt = 100 A/µs; - 43 - ns
Q
rr
Reverse recovery charge V
GS
= 0 V; V
R
= 30 V - 94 - nC
Fig.1. Normalised power dissipation.
PD% = 100
⋅
P
D
/P
D 25 ˚C
= f(T
mb
)
Fig.2. Normalised continuous drain current.
ID% = 100
⋅
I
D
/I
D 25 ˚C
= f(T
mb
); conditions: V
GS
≥
5 V
Fig.3. Safe operating area. T
mb
= 25 ˚C
I
D
& I
DM
= f(V
DS
); I
DM
single pulse; parameter t
p
Fig.4. Transient thermal impedance.
Z
th j-mb
= f(t); parameter D = t
p
/T
Normalised Power Derating, PD (%)
0
10
20
30
40
50
60
70
80
90
100
0 25 50 75 100 125 150 175
Mounting Base temperature, Tmb (C)
0.1
1
10
100
1 10 100
Drain-Source Voltage, VDS (V)
Peak Pulsed Drain Current, IDM (A)
D.C.
100 ms
10 ms
RDS(on) = VDS/ ID
1 ms
tp = 10 us
100 us
Normalised Current Derating, ID (%)
0
10
20
30
40
50
60
70
80
90
100
0 25 50 75 100 125 150 175
Mounting Base temperature, Tmb (C)
0.01
0.1
1
10
1E-06 1E-05 1E-04 1E-03 1E-02 1E-01 1E+00
Pulse width, tp (s)
Transient thermal impedance, Zth j-mb (K/W)
single pulse
D = 0.5
0.2
0.1
0.05
0.02
tp
D = tp/T
D
P
T
August 1999 3 Rev 1.500
Philips Semiconductors Product specification
N-channel TrenchMOS transistor PHP21N06LT, PHB21N06LT
Logic level FET PHD21N06LT
Fig.5. Typical output characteristics, T
j
= 25 ˚C
.
I
D
= f(V
DS
)
Fig.6. Typical on-state resistance, T
j
= 25 ˚C
.
R
DS(ON)
= f(I
D
)
Fig.7. Typical transfer characteristics.
I
D
= f(V
GS
)
Fig.8. Typical transconductance, T
j
= 25 ˚C
.
g
fs
= f(I
D
)
Fig.9. Normalised drain-source on-state resistance.
R
DS(ON)
/R
DS(ON)25 ˚C
= f(T
j
)
Fig.10. Gate threshold voltage.
V
GS(TO)
= f(T
j
); conditions: I
D
= 1 mA; V
DS
= V
GS
0
5
10
15
20
25
30
35
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
Drain-Source Voltage, VDS (V)
Drain Current, ID (A)
2.8 V
Tj = 25 C
VGS = 10V
3 V
3.2 V
3.4 V
2.4 V
5 V
2.6 V
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0 2 4 6 8 10 12 14 16 18 20
Drain current, ID (A)
Transconductance, gfs (S)
Tj = 25 C
175 C
VDS > ID X RDS(ON)
0
0.05
0.1
0.15
0.2
0.25
0.3
0 5 10 15 20 25 30 35
Drain Current, ID (A)
Drain-Source On Resistance, RDS(on) (Ohms)
VGS = 10V
Tj = 25 C
3.2 V
5 V
3.4 V
3 V
2.8V
2.6 V
2.4 V
Normalised On-state Resistance
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
2.2
2.4
-60 -40 -20 0 20 40 60 80 100 120 140 160 180
Junction temperature, Tj (C)
0
2
4
6
8
10
12
14
16
18
20
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
Gate-source voltage, VGS (V)
Drain current, ID (A)
VDS > ID X RDS(ON)
Tj = 25 C
175 C
Threshold Voltage, VGS(TO) (V)
0
0.25
0.5
0.75
1
1.25
1.5
1.75
2
2.25
-60 -40 -20 0 20 40 60 80 100 120 140 160 180
Junction Temperature, Tj (C)
typical
maximum
minimum
August 1999 4 Rev 1.500
Philips Semiconductors Product specification
N-channel TrenchMOS transistor PHP21N06LT, PHB21N06LT
Logic level FET PHD21N06LT
Fig.11. Sub-threshold drain current.
I
D
= f(V
GS)
; conditions: T
j
= 25 ˚C; V
DS
= V
GS
Fig.12. Typical capacitances, C
iss
, C
oss
, C
rss
.
C = f(V
DS
); conditions: V
GS
= 0 V; f = 1 MHz
Fig.13. Typical turn-on gate-charge characteristics.
V
GS
= f(Q
G
)
Fig.14. Typical reverse diode current.
I
F
= f(V
SDS
); conditions: V
GS
= 0 V; parameter T
j
Fig.15. Maximum permissible non-repetitive
avalanche current (I
AS
) versus avalanche time (t
AV
);
unclamped inductive load
Drain current, ID (A)
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
0 0.5 1 1.5 2 2.5 3
Gate-source voltage, VGS (V)
minimum
typical
maximum
0
5
10
15
20
25
30
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5
Source-Drain Voltage, VSDS (V)
Source-Drain Diode Current, IF (A)
Tj = 25 C
175 C
VGS = 0 V
10
100
1000
10000
0.1 1 10 100
Drain-Source Voltage, VDS (V)
Capacitances, Ciss, Coss, Crss (pF)
Ciss
Coss
Crss
0.1
1
10
100
0.001 0.01 0.1 1 10
Avalanche time, t
AV
(ms)
Maximum Avalanche Current, I
AS
(A)
Tj prior to avalanche = 150 C
25 C
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
02468101214161820
Gate charge, QG (nC)
Gate-source voltage, VGS (V)
ID = 20A
Tj = 25 C
VDD = 11 V
VDD = 44 V
August 1999 5 Rev 1.500
P1-P3P4-P6P7-P9P10-P12

PHD21N06LT,118

Mfr. #:
Buy PHD21N06LT,118
Manufacturer:
NXP Semiconductors
Description:
MOSFET N-CH 55V 19A DPAK
Lifecycle:
New from this manufacturer.
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