6.42
IDT70P265/255/245L
Low Power 16K/8K/4K x 16 Dual-Port Static RAM Industrial Temperature Range
18 SEPTEMBER 29, 2011
Truth Table III — Interrupt Flag
(1)
NOTES:
1. Assumes BUSY
L = BUSYR = VIH.
2. 3FFF for 70P265, 1FFF for 70P255, FFF for 70P245.
3. 3FFE for 70P265, 1FFE for 70P255, FFE for 70P245.
Left Port Right Port
Function
WE CS OE
L
A
13L
-A
0L
INT
L
WE CS OE
R
A
13R
-A
0R
INT
R
L L X 3FFF
(2)
XXXX X LSet Right INT
R
Flag
XXXXXXLL3FFF
(2)
H Reset Right INT
R
Flag
XXX X LLLX3FFE
(3)
X Set Left INT
L
Flag
X L L 3FFE
(3)
H X X X X X Reset Left INT
L
Flag
7145 tbl 16
Truth Table IV —
Address BUSY Arbitration
NOTES:
1. L if the inputs to the opposite port were stable prior to the address and enable inputs of this port. H if the inputs to the opposite port became stable after the address
and enable inputs of this port. If t
PS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs cannot be LOW simultaneously.
2. Writes to the left port are internally ignored when BUSY
L outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored
when BUSY
R outputs are driving LOW regardless of actual logic level on the pin.
Inputs Outputs
Function
CS
L
CS
R
Address Match
Left/Right Port
BUSY
L
BUSY
R
XXNO MATCH H H Normal
HX MATCH H H Normal
XH MATCH H H Normal
L L MATCH (1) (1) Write Inhibit
(2)
7145 tbl 17
