XRT91L33A
7
REV. 1.0.1 STS-12/STS-3 MULTIRATE CLOCK AND DATA RECOVERY UNIT
FIGURE 3. CONTROL DIAGRAM FOR SIGNAL DETECTION CIRCUIT AND PLL TEST OPERATION
2.6 Lock Detection
XRT91L33A features a PLL lock detection circuit. The lock detect (LOCK) output goes HIGH to indicate that
the PLL is locked to the serial data input and valid data and clock are present at the high-speed differential
output. The LOCK output will go LOW if either the LOCKTOREFN or the SIGD input is forced LOW.
Additionally, LOCK will also go low if the incoming data frequency is more than +/-500ppm away from the
reference clock frequency (REFCK x 32 in OC12 mode, REFCK x 8 in OC3 mode). When LOCK output is
driven LOW, the VCO is forced to lock to REFCK and then released to lock on the incoming data. If the
incoming data frequency remains outside the +/-500ppm window, the training mode is repeated. Debounce
logic stabilizes the LOCK output pin to stay LOW for incoming frequencies well beyond the +/-500ppm window.
2.7 Test Pin Functionality
The TEST pin on the XRT91L33A is a three-level control input - VDD, VSS and 1.4V. This pin determines the
test (bypass) mode operation and controls the bandwidth of the PLL. Pulling this pin low sets the high
bandwidth operation and is used for normal operation. Pulling this pin high sets the low bandwidth operation
that is used for improved SONET jitter transfer performance. Applying 1.4V to the input configures the device
into a bypass mode for use in production test.
2.7.1 Normal Operation
If the Test pin is held low the part functions normally with similar performance to the XRT91L33A. The PLL
bandwidth is configured for high bandwidth.
2.7.2 Improved Jitter Transfer Operation
If the Test pin is held high the part optimizes the SONET jitter transfer performance. This mode is offered for
applications where the jitter transfer characteristics are more critical. The PLL bandwidth is configured for low
bandwidth.
2.7.3 Bypass Mode Operation
If TEST is set to 1.4V and STS12_MODE pin is set to logic HIGH, XRT91L33A will bypass the PLL and present
an inverted version of the REFCK to the clock output RXCLKOP/N. REFCK’s rising edge is used to capture the
input data and transmit data to RXDOP/N. This bypass test operation can be used to facilitate board level
debugging process.
0
1
LOS (Internal)
SIGD
LOCKTOREFN
TEST
STS12_Mode
REFCK
PLL Clock
(Internal)
RXDIP/N
22
2
RXCLKOP/N
RXDOP/N
BW Select
(Internal)
