XRT91L33A
6
STS-12/STS-3 MULTIRATE CLOCK AND DATA RECOVERY UNIT REV. 1.0.1
2.0 FUNCTIONAL DESCRIPTION
The XRT91L33A CDR is designed to operate with a SONET Framer/ASIC device and provide a high-speed
serial clock and data recovery interface to optical networks. The CDR receives a differential NRZ serial bit
stream running at STS-12/STM-4 or STS-3/STM-1 and generates recovered serial clock and data via
differential LVDS/LVPECL drivers.
2.1 Reference Clock Input
The XRT91L33A accepts a 19.44 MHz LVTTL clock input at REFCK. The REFCK should be generated from a
source that has a frequency accuracy better than ±100ppm in order for the CDR Loss of Lock detector to have
the necessary accuracy required for SONET systems.
2.2 Receive Clock and Data Recovery
The clock and data recovery (CDR) unit accepts the high-speed NRZ serial data from the Differential receiver
and generates a clock that is the same frequency as the incoming data. The clock recovery block utilizes the
reference clock from REFCK to train and monitor its clock recovery PLL. Upon startup, the PLL locks to the
local reference clock. Once this is achieved, the PLL then attempts to lock onto the incoming receive serial
data stream. Whenever the recovered clock frequency deviates from the local reference clock frequency by
more than approximately ±500ppm, the clock recovery PLL will switch to the local reference clock, declare a
Loss of Lock and output a LOW level signal on the LOCK output pin. Whenever a Loss of Lock (LOL) or a Loss
of Signal (LOS) event occurs, the CDR will continue to supply a receive clock (based on the local reference).
2.3 External Receive Loop Filter Capacitor
For STS12/STM4 and STS3/STM1 operation, the XRT91L33A uses a 1.0uF external loop filter capacitor to
achieve the required receiver jitter performance. It must be well isolated to prohibit noise entering the CDR
block and should be placed as close to the pins as possible. The non-polarized capacitor should be of ±10%
tolerance. Use type X7R or X5R capacitors for improved stability over temperature.
2.4 STS-12/STM-4 and STS-3/STM-1 Mode of Operation
The VCO output signal is fed into a programmable frequency divider allowing one to properly set the PLL
operating frequency corresponding to the desired data rate. For 622.08 Mbps signal STS12_MODE is set
HIGH and for 155.52 Mbps, STS12_MODE is set LOW.
2.5 Signal Detection
XRT91L33A has two control pins that are used to indicate an LOS condition (Loss Of Signal). The SIGD pin is
a LVPECL input and the LCKTOREFN pin is a LVTTL input. They are internally connected as shown in Figure
3. If either of these two inputs goes LOW and TEST is LOW or HIGH, XRT91L33A will enter a Loss of Signal
(LOS) state, and will mute the RXDOP/N. During the LOS state, XRT91L33A will also maintain RXCLKOP/N
within ±500ppm of the input reference clock, REFCK. Most optical modules have an SIGD output. This SIGD
output indicates that there is sufficient optical power and is typically active HIGH. If the SIGD output on the
optical module is LVPECL, it should be connected directly to the SIGD input of XRT91L33A, and the
LCKTOREFN input should be tied HIGH. If the SIGD output is LVTTL, it should be connected directly to the
LCKTOREFN input and the SIGD input should be tied HIGH. The SIGD and LCKTOREFN inputs also can be
used for other applications when it is required to hold RXCLKOP/N output within ±500ppm of the input
reference clock and mute the serial data output lines.
