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LTC3729LEUH-6#TRPBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P28
13
LTC3729L-6
sn3729l6 3729l6fs
V
V
k
N
OUT
IN
=
where k = 1, 2, …, N – 1
So the number of phases used can be selected to minimize
the output ripple current and therefore the output ripple
voltage at the given input and output voltages. In applica-
tions having a highly varying input voltage, additional
phases will produce the best results.
Accepting larger values of ∆I
L
allows the use of low
inductances, but can result in higher output voltage ripple.
A reasonable starting point for setting ripple current is ∆I
L
= 0.4(I
OUT
)/N, where N is the number of channels and I
OUT
is the total load current. Remember, the maximum ∆I
L
occurs at the maximum input voltage. The individual
inductor ripple currents are constant determined by the
inductor, input and output voltages.
Ferrite designs have very low core loss and are preferred
at high switching frequencies, so design goals can con-
centrate on copper loss and preventing saturation. Ferrite
core material saturates “hard,” which means that induc-
tance collapses abruptly when the peak design current is
exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple.
Do
not allow the core to saturate!
Molypermalloy (from Magnetics, Inc.) is a very good, low
loss core material for toroids, but it is more expensive than
ferrite. A reasonable compromise from the same manu-
facturer is Kool Mµ. Toroids are very space efficient,
especially when you can use several layers of wire. Be-
cause they lack a bobbin, mounting is more difficult.
However, designs for surface mount are available which
do not increase the height significantly.
Power MOSFET, D1 and D2 Selection
Two external power MOSFETs must be selected for each
controller with the LTC3729L-6: One N-channel MOSFET
for the top (main) switch, and one N-channel MOSFET for
the bottom (synchronous) switch.
The peak-to-peak drive levels are set by the INTV
CC
volt-
age. This voltage is typically 5V during start-up (see
EXTV
CC
Pin Connection). Consequently, logic-level thresh-
old MOSFETs must be used in most applications. The only
exception is if low input voltage is expected (V
IN
< 5V);
then, sublogic-level threshold MOSFETs (V
GS(TH)
< 3V)
should be used. Pay close attention to the BV
DSS
specifi-
cation for the MOSFETs as well; most of the logic-level
MOSFETs are limited to 30V or less.
Selection criteria for the power MOSFETs include the “ON”
resistance R
DS(ON)
, Miller capacitance C
MILLER
, input volt-
age and maximum output current. Miller capacitance,
C
MILLER
, can be approximated from the gate charge curve
usually provided on the MOSFET manufacturers’ data
sheet. C
MILLER
is equal to the increase in gate charge along
the horizontal axis while the curve is approximately flat
divided by the specified change in V
DS
. This result is then
multiplied by the ratio of the application applied V
DS
to the
Gate charge curve specified V
DS
. When the IC is operating
in continuous mode the duty cycles for the top and bottom
MOSFETs are given by:
Kool Mµ is a registered trademark of Magnetics, Inc.
APPLICATIO S I FOR ATIO
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Figure 3. Normalized Peak Output Current vs
Duty Factor [I
RMS
≈ 0.3 (∆I
O(P–P)
)]
DUTY FACTOR (V
OUT
/V
IN
)
0.1 0.2 0.3 0.4
0.5 0.6 0.7 0.8 0.9
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
3729L-6 F03
6-PHASE
4-PHASE
3-PHASE
2-PHASE
1-PHASE
∆I
O(P-P)
V
O
/fL
Inductor Core Selection
Once the values for L1 and L2 are known, the type of
inductor must be selected. High efficiency converters
generally cannot afford the core loss found in low cost
powdered iron cores, forcing the use of more expensive
ferrite, molypermalloy, or Kool Mµ
®
cores. Actual core
loss is independent of core size for a fixed inductor value,
but it is very dependent on inductance selected. As induc-
tance increases, core losses go down. Unfortunately,
increased inductance requires more turns of wire and
therefore copper losses will increase.
14
LTC3729L-6
sn3729l6 3729l6fs
Main SwitchDuty Cycle
V
V
OUT
IN
=
Synchronous SwitchDuty Cycle
VV
V
IN OUT
IN
=
–
The MOSFET power dissipations at maximum output
current are given by:
P
V
V
IR
V
I
RC
VVV
f
MAIN
OUT
IN
MAX DS ON
IN
MAX
DR MILLER
INTVCC THMIN THMIN
=
()
+
()
+
()
()( )
+
()
2
2
1
2
11
δ
()
•
–
P
VV
V
I
N
R
SYNC
IN OUT
IN
MAX
DS ON
=
+
()
–
()
2
1 δ
where δ is the temperature dependency of R
DS(ON)
and
R
DR
(approximately 4Ω) is the effective driver resistance
at the MOSFET’s Miller threshold voltage. V
THMIN
is the
typical MOSFET minimum threshold voltage.
Both MOSFETs have I
2
R losses but the topside N-channel
equation includes an additional term for transition losses,
which peak at the highest input voltage. For V
IN
< 20V the
high current efficiency generally improves with larger
MOSFETs, while for V
IN
> 20V the transition losses rapidly
increase to the point that the use of a higher R
DS(ON)
device
with lower C
MILLER
actual provides higher efficiency. The
synchronous MOSFET losses are greatest at high input
voltage when the top switch duty factor is low or during a
short-circuit when the synchronous switch is on close to
100% of the period.
The term (1 + δ) is generally given for a MOSFET in the
form of a normalized R
DS(ON)
vs. Temperature curve, but
δ = 0.005/°C can be used as an approximation for low
voltage MOSFETs.
The Schottky diodes, D1 and D2 shown in Figure 1 conduct
during the dead-time between the conduction of the two
large power MOSFETs. This helps prevent the body diode
of the bottom MOSFET from turning on, storing charge
during the dead-time, and requiring a reverse recovery
period which would reduce efficiency. A 1A to 3A (depend-
ing on output current) Schottky diode is generally a good
compromise for both regions of operation due to the
relatively small average current. Larger diodes result in
additional transition losses due to their larger junction
capacitance.
C
IN
and C
OUT
Selection
In continuous mode, the source current of each top
N-channel MOSFET is a square wave of duty cycle V
OUT
/
V
IN
. A low ESR input capacitor sized for the maximum
RMS current must be used. The details of a close form
equation can be found in Application Note 77. Figure 4
shows the input capacitor ripple current for different
phase configurations with the output voltage fixed and
input voltage varied. The input ripple current is normalized
against the DC output current. The graph can be used in
place of tedious calculations. The minimum input ripple
current can be achieved when the product of phase num-
ber and output voltage, N(V
OUT
), is approximately equal to
the input voltage V
IN
or:
V
V
k
N
OUT
IN
=
where k = 1, 2, …, N – 1
So the phase number can be chosen to minimize the input
capacitor size for the given input and output voltages.
In the graph of Figure 4, the local maximum input RMS
capacitor currents are reached when:
V
V
k
N
OUT
IN
=
−21
2
where k = 1, 2, …, N
These worst-case conditions are commonly used for
design because even significant deviations do not offer
much relief. Note that capacitor manufacturer’s ripple
current ratings are often based on only 2000 hours of life.
This makes it advisable to further derate the capacitor, or
to choose a capacitor rated at a higher temperature than
APPLICATIO S I FOR ATIO
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15
LTC3729L-6
sn3729l6 3729l6fs
required. Several capacitors may also be paralleled to
meet size or height requirements in the design. Always
consult the capacitor manufacturer if there is any ques-
tion.
The graph shows that the peak RMS input current is
reduced linearly, inversely proportional to the number, N
of stages used. It is important to note that the efficiency
loss is proportional to the input RMS current
squared
and
therefore a 2-stage implementation results in 75% less
power loss when compared to a single phase design.
Battery/input protection fuse resistance (if used), PC
board trace and connector resistance losses are also
reduced by the reduction of the input ripple current in a
PolyPhase system. The required amount of input capaci-
tance is further reduced by the factor, N, due to the
effective increase in the frequency of the current pulses.
The selection of C
OUT
is driven by the required effective
series resistance (ESR). Typically once the ESR require-
ment has been met, the RMS current rating generally far
exceeds the I
RIPPLE(P-P)
requirements. The steady state
output ripple (∆V
OUT
) is determined by:
∆∆V I ESR
NfC
OUT RIPPLE
OUT
≈+
1
8
Where f = operating frequency of each stage, N is the
number of phases, C
OUT
= output capacitance, and
∆I
RIPPLE
= combined inductor ripple currents.
The output ripple varies with input voltage since ∆I
L
is a
function of input voltage. The output ripple will be less than
50mV at max V
IN
with ∆I
L
= 0.4I
OUT(MAX)
/N assuming:
C
OUT
required ESR < 2N(R
SENSE
) and
C
OUT
> 1/(8Nf)(R
SENSE
)
The emergence of very low ESR capacitors in small,
surface mount packages makes very physically small
implementations possible. The ability to externally com-
pensate the switching regulator loop using the I
TH
pin(OPTI-
LOOP compensation) allows a much wider selection of
output capacitor types. OPTI-LOOP compensation effec-
tively removes constraints on output capacitor ESR. The
impedance characteristics of each capacitor type are sig-
nificantly different than an ideal capacitor and therefore
require accurate modeling or bench evaluation during
design.
Manufacturers such as Nichicon, United Chemicon and
Sanyo should be considered for high performance through-
hole capacitors. The OS-CON semiconductor dielectric
capacitor available from Sanyo and the Panasonic SP
surface mount types have the lowest (ESR)(size) product
of any aluminum electrolytic at a somewhat higher price.
An additional ceramic capacitor in parallel with OS-CON
type capacitors is recommended to reduce the inductance
effects.
In surface mount applications, multiple capacitors may
have to be paralleled to meet the ESR or RMS current
handling requirements of the application. Aluminum elec-
trolytic and dry tantalum capacitors are both available in
surface mount configurations. New special polymer sur-
face mount capacitors offer very low ESR also but have
much lower capacitive density per unit volume. In the case
of tantalum, it is critical that the capacitors are surge tested
for use in switching power supplies. Several excellent
choices are the AVX TPS, AVX TPSV or the KEMET T510
series of surface mount tantalums, available in case heights
ranging from 2mm to 4mm. Other capacitor types include
Sanyo OS-CON, Nichicon PL series and Sprague 595D
series. Consult the manufacturer for other specific recom-
mendations. A combination of capacitors will often result
in maximizing performance and minimizing overall cost
and size.
APPLICATIO S I FOR ATIO
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Figure 4. Normalized Input RMS Ripple Current vs
Duty Factor for 1 to 6 Output Stages
DUTY FACTOR (V
OUT
/V
IN
)
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
0.9
0.6
0.5
0.4
0.3
0.2
0.1
0
3729L-6 F04
RMS INPUT RIPPLE CURRNET
DC LOAD CURRENT
6-PHASE
4-PHASE
3-PHASE
2-PHASE
1-PHASE
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LTC3729LEUH-6#TRPBF

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Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators PolyPhase Controller QFN Package with 0.6V ref
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