RT9724
10
DS9724-02 July 2012www.richtek.com
©
Copyright 2012 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.
The resistance of the switch is defined as follows :
R
SWITCH
= { 4.75V − 4.4V − [ 0.5A x ( 4 x 30mΩ + 2 x
90mΩ) ] − V
PCB
}
÷
( 0.1A x N
PORTS
)
= (200mV − V
PCB
)
÷
( 0.1A x N
PORTS
)
If the voltage drop across the PCB is limited to 100mV,
the maximum resistance for the switch is 250mΩ for four
ports ganged together. The RT9724, with its maximum
100mΩ on-resistance over temperature, can fit the demand
of this requirement.
Thermal Shutdown
Thermal protection limits the power dissipation in the
RT9724. When the operation junction temperature
exceeds 130°C, the OTP circuit starts the thermal
shutdown function and turns the pass element off. The
pass element turn on again after the junction temperature
cools to 80°C. The RT9724 lowers its OTP trip level from
130°C to 100°C when output short circuit occurs (V
OUT
<
1V) as shown in Figure 1.
Figure 1. Short Circuit Thermal Folded Back Protection
when Output Short Circuit Occurs (Patent)
V
OUT
Short to GND
1V
V
OUT
I
OUT
Thermal
Shutdown
OTP Trip Point
130 C
°
110 C
°
100 C
°
80 C
°
IC Temperature
Thermal Considerations
The maximum power dissipation depends on the thermal
resistance of IC package, PCB layout, the rate of
surroundings airflow and temperature difference between
junction to ambient. The maximum power dissipation can
be calculated by following formula :
P
D(MAX)
= (T
J(MAX)
− T
A
) / θ
JA
where T
J(MAX)
is the maximum junction temperature, T
A
is
the ambient temperature, and θ
JA
is the junction to ambient
thermal resistance.
For recommended operating conditions specification, the
maximum junction temperature is 125°C. The junction to
ambient thermal resistance θ
JA
is layout dependent. For
SOT-23-5 package, the thermal resistance θ
JA
is
218.1°C/W on the standard JEDEC 51-7 four layers
thermal test board. For WDFN-8L 2x2 package, the
thermal resistance θ
JA
is 120°C/W on the standard JEDEC
51-7 four layers thermal test board. The maximum power
dissipation at T
A
= 25°C can be calculated by following
formula :
P
D(MAX)
= (125°C − 25°C) / (218.1°C/W) = 0.458W for
SOT-23-5 package
P
D(MAX)
= (125°C − 25°C) / (120°C/W) = 0.833W for
WDFN-8L 2x2 package
The maximum power dissipation depends on operating
ambient temperature for fixed T
J(MAX)
and thermal
resistance θ
JA
. The Figure 2 of derating curves allows the
designer to see the effect of rising ambient temperature
on the maximum power allowed.
Figure 2. Derating Curve of Maximum Power Dissipation
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0255075100125
Ambient Temperature (°C)
Maximum Power Dissipation (W
WDFN-8L 2x2
SOT-23-5
Single Layer PCB
