Semiconductor Components Industries, LLC, 2000
August, 2000 – Rev. 4
1 Publication Order Number:
MC14014B/D
MC14014B, MC14021B
8-Bit Static Shift Register
The MC14014B and MC14021B 8–bit static shift registers are
constructed with MOS P–channel and N–channel enhancement mode
devices in a single monolithic structure. These shift registers find
primary use in parallel–to–serial data conversion, synchronous and
asynchronous parallel input, serial output data queueing; and other
general purpose register applications requiring low power and/or high
noise immunity.
• Synchronous Parallel Input/Serial Output (MC14014B)
• Asynchronous Parallel Input/Serial Output (MC14021B)
• Synchronous Serial Input/Serial Output
• Full Static Operation
• “Q” Outputs from Sixth, Seventh, and Eighth Stages
• Double Diode Input Protection
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range
• MC14014B Pin–for–Pin Replacement for CD4014B
• MC14021B Pin–for–Pin Replacement for CD4021B
MAXIMUM RATINGS (Voltages Referenced to V
SS
) (Note 2.)
Symbol
Parameter Value Unit
V
DD
DC Supply Voltage Range –0.5 to +18.0 V
V
in
, V
out
Input or Output Voltage Range
(DC or Transient)
–0.5 to V
DD
+ 0.5 V
I
in
, I
out
Input or Output Current
(DC or Transient) per Pin
±10 mA
P
D
Power Dissipation,
per Package (Note 3.)
500 mW
T
A
Ambient Temperature Range –55 to +125 °C
T
stg
Storage Temperature Range –65 to +150 °C
T
L
Lead Temperature
(8–Second Soldering)
260 °C
2. Maximum Ratings are those values beyond which damage to the device
may occur.
3. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/C From 65C To 125C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high–impedance circuit. For proper operation, V
in
and V
out
should be constrained
to the range V
SS
(V
in
or V
out
) V
DD
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V
SS
or V
DD
). Unused outputs must be left open.
http://onsemi.com
xx = Specific Device Code
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
Device Package Shipping
ORDERING INFORMATION
MC14014BCP PDIP–16 2000/Box
MC14014BD SOIC–16 48/Rail
MC14014BDR2 SOIC–16 2500/Tape & Reel
1. For ordering information on the EIAJ version of
the SOIC packages, please contact your local
ON Semiconductor representative.
MARKING
DIAGRAMS
1
16
PDIP–16
P SUFFIX
CASE 648
MC140xxBCP
AWLYYWW
SOIC–16
D SUFFIX
CASE 751B
1
16
140xxB
AWLYWW
SOEIAJ–16
F SUFFIX
CASE 966
1
16
MC140xxB
ALYW
MC14014BF SOEIAJ–16 See Note 1.
MC14014BFEL SOEIAJ–16 See Note 1.
MC14021BCP PDIP–16 2000/Box
MC14021BD SOIC–16 48/Rail
MC14021BDR2 SOIC–16 2500/Tape & Reel
MC14021BF SOEIAJ–16 See Note 1.
MC14021BFEL SOEIAJ–16 See Note 1.
